View DS2148T_4287849.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 of 75 rev: 082504 features complete e1, t1, or j1 line interface unit (liu) supports both long- and short-haul trunks internal software-selectable receive-side termination for 75 ? /100 ? /120 5v power supply 32-bit or 128-bit crysta l-less jitter attenuator requires only a 2.048mhz master clock for both e1 and t1 with option to use 1.544mhz for t1 generates the appropriate line build outs, with and without return loss, for e1 and dsx-1 and csu line build outs for t1 ami, hdb3, and b8zs, encoding/decoding 16.384mhz, 8.192mhz, 4.096mhz, or 2.048mhz clock output synthesized to recovered clock programmable monitor mode for receiver loopbacks and prbs pattern generation/ detection with output for received errors generates/detects in-ban d loop codes, 1 to 16 bits including csu loop codes 8-bit parallel or serial interface with optional hardware mode multiplexed and nonmultip lexed parallel bus supports intel or motorola detects/generates blue (ais) alarms nrz/bipolar interface for tx/rx data i/o transmit open-circuit detection receive carrier loss (rcl) indication (g.775) high-z state for ttip and tring 50ma (rms) current limiter pin description ordering information single-channel devices: DS2148Tn 44-pin tqfp (-40 c to +85 c) DS2148T 44-pin tqfp (0 c to +70 c) ds2148gn 7mm cabga (-40 c to +85 c) ds2148g 7mm cabga (0 c to +70 c) four-channel devices: ds21q48n (quad) bga (-40 c to +85 c) ds21q48 (quad) bga (0 c to +70 c) 44 tqfp 7mm cabga 1 44 ds2148/ds21q48 5v e1/t1/j1 line interface www.maxim-ic.com
ds2148/q48 2 of 75 description the ds2148 is a complete selectable e1 or t1 li ne interface unit (liu) for short- and long-haul applications. throughout the data sheet, j1 is repres ented wherever t1 exists. receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0db to 12db or 0db to 43db for e1 applications and 0db to 30db or 0db to 36db for t1 applications. the device can generate the necessary g.703 e1 waveshapes in 75 ? or 120 ? applications and dsx-1 line build outs or csu line build outs of 0db, -7.5db, -15db, and -22.5db for t1 applications. the crystal-less onboard jitter attenuator requires only a 2.048mhz mclk for both e1 and t1 applications (with the option of using a 1.544mhz mclk in t1 applications). the jitter attenua tor fifo is selectable to either 32 bits or 128 bits in depth and can be placed in either the transmit or receive data paths. an x 2.048mhz output clock synthesized to rclk is available for use as a backpl ane system clock (where n = 1, 2, 4, or 8). the ds2148 has diagnostic capabilities such as loopbacks and prbs pattern generation/detection. 16- bit loop-up and loop-down codes can be generated and detected. the device can be controlled via an 8-bit parallel muxed or nonmuxed port, serial port or used in hardware mode. the device fully meets all of the latest e1 and t1 specifications including ansi t1.403-1999, ansi t1.408, at&t tr 62411, itu g.703, g.704, g.706, g.736, g.775, g.823, i.431, o.151, o.161, etsi ets 300 166, jtg.703, jti.431, jj-20.1, tbr12, tbr13, and ctr4.
ds2148/q48 3 of 75 table of contents 1. list of figures............................................................................................................. .................. 4 2. list of tables .............................................................................................................. .................. 5 3. introduction................................................................................................................ ................. 6 3.1 document revision history ............................................................................................ 6 4. pin description ............................................................................................................. ................ 9 5. hardware mode ............................................................................................................... .......... 22 5.1 register map ............................................................................................................... ........... 23 5.2 parallel port operation................................................................................................ 24 5.3 serial port operation ...................................................................................................... 24 6. control registers........................................................................................................... ......... 28 6.1 device power-up and reset ............................................................................................ 31 7 status registers ............................................................................................................. .......... 34 8. diagnostics ................................................................................................................. ................. 39 8.1 in-band loop code ge neration and detection ................................................... 39 8.2 loopbacks .................................................................................................................. ............. 43 8.2.1 remote loopback (rlb).................................................................................................... ..... 43 8.2.2 local loopback (llb)..................................................................................................... ....... 43 8.2.3 analog loopback (llb) .................................................................................................... ..... 44 8.2.4 dual loopback (dlb) ...................................................................................................... ...... 44 8.3 prbs generation and detection ................................................................................. 44 8.4 error counter.............................................................................................................. ........ 44 8.4.1 error counter update ..................................................................................................... ....... 45 8.5 error insertion............................................................................................................ ........ 45 9. analog interface ............................................................................................................ ......... 46 9.1 receiver ................................................................................................................ .................... 46 9.2 transmitter ............................................................................................................ ............... 47 9.3 jitter attenuator ...................................................................................................... ........ 47 9.4 g.703 synchronization signal ...................................................................................... 48 10. ds21q48 quad liu........................................................................................................... .............. 56 11. dc characteristics......................................................................................................... ......... 60 12. ac characteristics......................................................................................................... ......... 62 13. mechanical dimensions...................................................................................................... ... 71 13.1 mechanical dimensions?quad version................................................................. 73
ds2148/q48 4 of 75 1. list of figures figure 3-1 ds2148 block diagram................................................................................................ ..... 7 figure 3-2 receive logic ....................................................................................................... ............... 8 figure 3-3 transmit logic ...................................................................................................... ............. 9 figure 4-1 parallel port mode pinout (bis1 = 0, bis0 = 1 or 0) ............................................ 21 figure 4-2 serial port mode pinout (bis1 = 1, bis0 = 0) .......................................................... 21 figure 4-3 hardware mode pinout (bis1 = 1, bis0 = 1) ............................................................ 22 figure 5-1 serial port operation for read access (r=1) mode 1.................................. 25 figure 5-2 serial port operation for read access mode 2 ............................................. 25 figure 5-3 serial port operation for read access mode 3 ............................................. 26 figure 5-4 serial port operation for read access mode 4 ............................................. 26 figure 5-5 serial port operation for write access (r=0) modes 1&2 ...?????27 figure 5-6 serial port operation for write access modes 3&4 ????...????27 figure 9-1 basic interface ???????????????????????????..50 figure 9-2 protected interface using internal receive termination.................... 51 figure 9-3 protected interface using external receive termination .................. 52 figure 9-4 e1 transmit pulse template...................................................................................... 53 figure 9-5 t1 transmit pulse template...................................................................................... 54 figure 9-6 jitter tolerance.................................................................................................... ......... 55 figure 9-7 jitter attenuation ........................................................................................................ 55 figure 10-1 bga 12 x 12 pin layout ............................................................................................. ..... 59 figure 12-1 intel bus read timing (pbts = 0, bis1 = 0, bis0 = 0) ............................................ 63 figure 12-2 intel bus write timing (pbts = 0, bis1 = 0, bis0 = 0)........................................... 63 figure 12-3 motorola bus timing (pbts = 1, bis1 = 0, bis0 = 0) ............................................ 64 figure 12-4 intel bus read timing (pbts = 0, bis1 = 0, bis0 = 1) ............................................ 66 figure 12-5 intel bus write timing (pbts = 0, bis1 = 0, bis0 = 1)........................................... 66 figure 12-6 motorola bus read timing (pbts = 1, bis1 = 0, bis0 = 1) ................................. 67 figure 12-7 motorola bus write timing (pbts = 1, bis1 = 0, bis0 = 1)................................ 67 figure 12-8 serial bus timing (bis1 = 1, bis0 = 0)........................................................................ 68 figure 12-9 receive side timing ................................................................................................ ...... 69 figure 12-10 transmit side timing.............................................................................................. ... 70
ds2148/q48 5 of 75 2. list of tables table 4-1 bus interface selection .............................................................................................. .. 9 table 4-2a pi n assignment...................................................................................................... ........... 10 table 4-2b pin descriptions (sorted by pin name, DS2148T pin numbering) ............................... 11 table 4-3a pin assignment in serial port mode..................................................................... 13 table 4-3b pin descriptions in serial po rt mode (sorted by pin name, DS2148T pin numbering) ..................................................................................................................... ..................... 14 table 4-4a pin assignmen t in hardware mode....................................................................... 16 table 4-4b pin descriptions in hardware mode (sorted by pin name, DS2148T pin numbering) ..................................................................................................................... ..................... 16 table 4-5 loopback control in hardware mode ................................................................ 20 table 4-6 transmit data control in hardware mode ..................................................... 20 table 4-7 receive sensitivity settings...................................................................................... 20 table 4-8 monitor gain settings ................................................................................................ .. 20 table 4-9 internal rx termination select............................................................................. 20 table 4-10 mclk selection...................................................................................................... .......... 20 table 5-1 register map ......................................................................................................... .............. 23 table 6-1 mclk selection....................................................................................................... ........... 29 table 6-2 receive sensitivity settings...................................................................................... 31 table 6-3 back plane clock select............................................................................................. 3 2 table 6-4 monitor gain settings ................................................................................................ .. 32 table 6-5 internal rx termination select............................................................................. 33 table 7-1 received alarm criteria ............................................................................................. 3 5 table 7-2 receive level indication............................................................................................. 38 table 8-1 transmit code length................................................................................................. .. 40 table 8-2 receive code length .................................................................................................. .... 40 table 8-3 definition of received errors.................................................................................. 44 table 8-4 function of ecrs bits and rneg pin ........................................................................ 45 table 9-1 line build out select for e1 in register ccr4 (ets = 0) ................................. 48 table 9-2 line build out select for t1 in register ccr4 (ets = 1) ................................. 48 table 9-3 transformer specifications for 5v operation ............................................... 49 table 10-1 ds21q48 pin assignment.............................................................................................. .. 56
ds2148/q48 6 of 75 3. introduction the analog ami/hdb3 waveform off the e1 line or the ami/b8zs waveform off the t1 line is transformer coupled into the rtip and rring pi ns of the ds2148. the user has the option to use internal software-selectable receive-side termination for 75 ? /100 ? /120 applications or external termination. the device recovers clock and data fro m the analog signal and passes it through the jitter attenuation mux outputting the received line clock at rclk and bipolar or nrz data at rpos and rneg. the ds2148 contains an active filter that recons tructs the analog-received signal for the nonlinear losses that occur in transmission. the receive circ uitry also is configurable for various monitor applications. the device has a usable receive sensitiv ity of 0db to -43db (e1) and 0db to -36db (t1), which allows the device to ope rate on 0.63mm (22awg) cables up to 2.5km (e1) and 6k feet (t1) in length. data input at tpos and tneg is sent via the jitter attenuation mux to the waveshaping circuitry and line driver. the ds2148 will drive the e1 or t1 line from the ttip and tring pins via a coupling transformer. the line driver can handle both cept 30/isdn-pri lines for e1 and long-haul (csu) or short-haul (dsx-1) lines for t1. 3.1 document revision history 1) 100 /60 termination reversed in internal rx termination select tables, 091799. 2) add ds21q48 pinout, 092899. 3) correct vsm pin number in q48 (12 x 12 bga) from g5 to g4, 120699. 4) add timing diagram for status register (write access mode); add mechanical dimensions for the quad version, 032900. 5) timing diagram for status register (write access mode) added; elaboration on burst mode bit; add mechanical dimensions for the quad version, 050300. 6) changes to datasheet to indicate 5v only part, 011801. 7) added supply current measurement; added th ermal characteristics of quad package, 092001. 8) corrected typos and removed instances of 3v operation, 082504.
ds2148/q48 7 of 75 ds2148 block diagram figure 3-1 v d d v s s p o w e r c o n n e c t i o n s 2 2 v c o / p l l m c l k 2.048mhz to 1.544mhz pll jitter attenuator mux vsm a n a l o g l o o p b a c k l i n e d r i v e r s c s u f i l t e r s w a v e s h a p i n g l o c a l l o o p b a c k t r i n g t t i p j i t t e r a t t e n u a t i o n ( c a n b e p l a c e d i n e i t h e r t r a n s m i t o r r e c e i v e p a t h ) f i l t e r p e a k d e t e c t c l o c k / d a t a r e c o v e r y r r i n g r t i p optional termination remote loopback (dual mode) unframed all ones insertion d 0 t o d 7 / a d 0 t o a d 7 p b t s w r * ( r / w * ) r d * ( d s * ) a l e ( a s ) a 0 t o a 4 8 5 s d o s d i s c l k i n t * c s * 2 1 b i s 0 b i s 1 c o n t r o l a n d t e s t p o r t ( r o u t e d t o a l l b l o c k s ) m u x ( t h e s e r i a l , p a r a l l e l , a n d h a r d w a r e i n t e r f a c e s s h a r e d e v i c e p i n s ) hrst* test 16.384mhz or 8.192mhz or 4.096mhz or 2.048mhz synthesizer bpclk rpos rclk rneg tpos tclk tneg jaclk mux see figure 3-2 see figure 3-3 pbeo h a r d w a r e i n t e r f a c e c o n t r o l a n d i n t e r r u p t p a r a l l e l i n t e r f a c e s e r i a l i n t e r f a c e r e m o t e l o o p b a c k mux rcl/lotc
ds2148/q48 8 of 75 receive logic figure 3-2 rpos rneg from remote loopback clock invert rclk ccr2.0 ccr1.6 routed to all blocks rx bd mux 4 or 8 zero detect 16 zero detect rir1.7 rir1.6 b8zs/hdb3 decoder all ones detector loop code detector prbs detector sr.6 sr.7 sr.4 rir1.3 ccr2.3 rir1.5 16-bit error counter (ecr) mux ccr6.0 sr.0 ccr6.2/ ccr6.0/ ccr6.1 nrz data bpv/cv/exz pbeo ccr1.4
ds2148/q48 9 of 75 transmit logic figure 3-3 4. pin description the ds2148 can be controlled in a para llel port mode, a serial port mode, or a hardware mode (table 4-1, 4-2, and 4-3). the parallel and serial port modes are described in sec tion 3, and the hardware mode is described below. bus interface selection table 4-1 bis1 bis0 pbts bus interface type 0 0 0 muxed intel 0 0 1 muxed motorola 0 1 0 nonmuxed intel 0 1 1 nonmuxed motorola 1 0 - serial port 1 1 - hardware bpv insert mux b8zs/ hdb3 coder logic error insert mux or gate or gate ccr3.1 ccr1.6 ccr2.2 ccr3.0 ccr3.4 ccr3.3 tpos tneg to remote loopback prbs generator loop code generator clock invert loss of transmit clock detect tclk ccr2.1 rclk jaclk (derived from mclk) ccr1.0 ccr1.1 ccr1.2 1 0 mux mux or gate to lotc output pin 0 1 0 1 and gate routed to all blocks tx bd sr.5
ds2148/q48 10 of 75 pin assignment in parallel port mode table 4-2a DS2148T pin # ds2148g pin# i/o parallel port mode 1 c3 i cs* 2 c2 i rd*(ds*) 3 b1 i wr*(r/w*) 4 d2 i ale(as) 5 c1 i na 6 d3 i na 7 d1 i/o a4 8 e1 i a3 9 f2 i a2 10 f1 i a1 11 g1 i a0 12 e3 i/o d7/ad7 13 f3 i/o d6/ad6 14 g2 i/o d5/ad5 15 f4 i/o d4/ad4 16 g3 i/o d3/ad3 17 e4 i/o d2/ad2 18 g4 i/o d1/ad1 19 f5 i/o d0/ad0 20 g5 i vsm 21 f6 - v dd 22 g6 - v ss 23 e5 i/o int* 24 e6 o pbeo 25 f7 o rcl/lotc 26 d6 i test 27 d5 i rtip 28 d7 i rring 29 c6 i hrst* 30 c7 i mclk 31 b6 o bpclk 32 b7 i bis0 33 a7 i bis1 34 c5 o ttip 35 b5 - v ss 36 a6 - v dd 37 b4 o tring 38 c4 o rpos 39 a4 o rneg 40 b3 o rclk 41 a3 i tpos 42 b2 i tneg 43 a2 i tclk 44 a1 i pbts
ds2148/q48 11 of 75 pin descriptions in parallel port mode (sorted by pin name, DS2148T pin numbering) table 4-2b acronym pin i/o description a0 to a4 11 to 7 i address bus. in nonmultiplexed bus operation (bis1 = 0, bis0 = 1), serves as the address bus. in multiplexed bus operation (bis1 = 0, bis0 = 0), these pins are not used and should be tied low. ale (as) 4 i address latch enable (address strobe). when using the parallel port (bis1 = 0) in multiplexed bus mode (bis0 = 0), serves to demultiplex the bus on a positive-going edge. in nonmultiplexed bus mode (bis0 = 1), should be tied low. bis0/ bis1 32/ 33 i bus interface select bits 0 & 1. used to select bus interface option. see table 4-1 for details. bpclk 31 o back plane clock. a 16.384mhz, 8.192mhz, 4.096mhz, or 2.048mhz clock output that is referenced to rclk selectable via ccr5.7 and ccr5.6. in hardware mode, defaults to 16.384mhz output. cs* 1 i chip select. must be low to read or wr ite to the device. cs* is an active low signal. d0 / ad0 to d7 / ad7 19 to 12 i/o data bus/address/data bus. in non-multiplexed bus operation (bis1 = 0, bis0 = 1), serves as the data bus. in multiplexed bus operation (bis1 = 0, bis0 = 0), serves as an 8-bit multiplexed address/data bus. hrst* 29 i hardware reset. bringing hrst* low will reset the ds2148 setting all control bits to their default state of all zeros. int* 23 o interrupt [int*] pin 23. flags host controller during conditions and change of conditions defined in the status register. active low, open drain output. mclk 30 i master clock. a 2.048mhz (50ppm) clock source with ttl levels is applied at this pin. this clock is used internally for both clock/data recovery and for jitte r attenuation. use of a t1 1.544mhz clock source is optional. see note 1 on clock accuracy at the end of this table. na - i not assigned. should be tied low. pbeo 24 o prbs bit error output. the receiver will constantly search for a 2 15 -1 or a 2 20 -1 prbs depending on the ets bit setting (ccr1.7). remains high if out of synchroniza tion with the prbs pattern. goes low when synchronized to the prbs pattern. any errors in the received pattern after synchroni zation will cause a positive going pulse (with same period as e1 or t1 clock) synchronous with rclk. prbs bit errors can also be reported to the ecr1 and ecr2 registers by setting ccr6.2 to a logic 1. pbts 44 i parallel bus type select. when using the parallel port (bis1 = 0), set high to select motorola bus timing, set low to select intel bus timing. this pin controls the function of the rd*(ds*), ale(as), and wr*(r/w*) pins. if pbts = 1 and bis1 = 0, then these pins assume the motorola function listed in parenthesis (). in serial port mode, this pin should be tied low.
ds2148/q48 12 of 75 acronym pin i/o description rclk 40 o receive clock. buffered recovered clock from the line. synchronous to mclk in absence of signal at rtip and rring. rd* (ds*) 2 i read input (data strobe). rd* and ds* are active low signals. ds active low when in nonmultiplexed, motorola mode. see the bus timing diagrams in section 12. rcl/ lotc 25 o receive carrier loss/loss of transmit clock. an output which will toggle high during a receive carrier loss (ccr2.7 = 0) or will toggle high if the tclk pin has not been toggled for 5 sec 2 sec (ccr2.7 = 1). ccr2.7 defaults to logic 0 when in hardware mode. rneg 39 o receive negative data. updated on the rising edge (ccr2.0 = 0) or the falling edge (ccr2.0 = 1) of rclk with the bipolar data out of the line interface. set nrze (ccr1.6) to a one for nrz applications. in nrz mode, data will be output on rpos while a received error will cause a positive-going pulse synchronous with rclk at rneg. see section 8.4 for details. rpos 38 o receive positive data. updated on the rising edge (ccr2.0 = 0) or the falling edge (ccr2.0 = 1) of rclk with bipolar data out of the line interface. set nrze (ccr1.6) to a one for nrz applications. in nrz mode, data will be output on rpos while a received error will cause a positive-going pulse synchronous with rclk at rneg. see section 8.4 for details. rtip/ rring 27/ 28 i receive tip and ring. analog inputs for clock recovery circuitry. these pins connect via a 1:1 transf ormer to the line. see section 7 for details. tclk 43 i transmit clock. a 2.048mhz or 1.544mhz primary clock. used to clock data through the transmit side formatter. can be sourced internally by mclk or rclk. see common control register 1 and figure 3-3. test 26 i 3-state control. set high to 3-state all outputs and i/o pins (including the parallel control port). set low for normal operation. useful in board level testing. tneg 42 i transmit negative data. sampled on the falling edge (ccr2.1 = 0) or the rising edge (ccr2.1 = 1) of tclk for data to be transmitted out onto the line. tpos 41 i transmit positive data. sampled on the falling edge (ccr2.1 = 0) or the rising edge (ccr2.1 = 1) of tclk for data to be transmitted out onto the line. ttip/ tring 34/ 37 o transmit tip and ring [ttip & tring]. analog line driver outputs. these pins connect via a st ep-up transformer to the line. see section 7 for details. v dd 21/ 36 - positive supply. 5.0v 5% vsm 20 i voltage supply mode. should be tied high for 5v operation v ss 22/ 35 - signal ground. wr* (r/w*) 3 i write input (read/write). wr* is an active low signal. see the bus timing diagrams in section 12.
ds2148/q48 13 of 75 pin assignment in serial port mode table 4-3a DS2148T pin # ds2148g pin# i/o serial port mode 1 c3 i cs* 2 c2 i na 3 b1 i na 4 d2 i na 5 c1 i sclk 6 d3 i sdi 7 d1 i/o sdo 8 e1 i ices 9 f2 i oces 10 f1 i na 11 g1 i na 12 e3 i/o na 13 f3 i/o na 14 g2 i/o na 15 f4 i/o na 16 g3 i/o na 17 e4 i/o na 18 g4 i/o na 19 f5 i/o na 20 g5 i vsm 21 f6 - v dd 22 g6 - v ss 23 e5 i/o int* 24 e6 o pbeo 25 f7 o rcl/lotc 26 d6 i test 27 d5 i rtip 28 d7 i rring 29 c6 i hrst* 30 c7 i mclk 31 b6 o bpclk 32 b7 i bis0 33 a7 i bis1 34 c5 o ttip 35 b5 - v ss 36 a6 - v dd 37 b4 o tring 38 c4 o rpos 39 a4 o rneg 40 b3 o rclk 41 a3 i tpos 42 b2 i tneg 43 a2 i tclk 44 a1 i na
ds2148/q48 14 of 75 pin descriptions in serial port mode (sorted by pin name, DS2148T pin numbering) table 4-3b acronym pin i/o description bis0/ bis1 32/ 33 i bus interface select bits 0 & 1. used to select bus interface option. see table 4-1 for details. bpclk 31 o back plane clock. a 16.384mhz, 8.192mhz, 4.096mhz, or 2.048mhz clock output that is refe renced to rclk selectable via ccr5.7 and ccr5.6. in hardware mode, defaults to 16.384mhz output. cs* 1 i chip select. must be low to read or write to the device. cs* is an active low signal. hrst* 29 i hardware reset. bringing hrst* low will reset the ds2148 setting all control bits to their default state of all zeros. ices 8 i input clock edge select. selects whether the serial port data input (sdi) is sampled on rising (ices =0) or falling edge (ices = 1) of sclk. int* 23 o interrupt [int*] pin 23. flags host controller during conditions and change of conditions defined in the status register. active low, open drain output. mclk 30 i master clock. a 2.048mhz (50ppm) clock source with ttl levels is applied at this pin. this clock is used internally for both clock/data recovery and for jitte r attenuation. use of a t1 1.544mhz clock source is optional. see note 1 on clock accuracy at the end of this table. na - i not assigned. should be tied low. oces 9 i output clock edge select. selects whether the serial port data output (sdo) is valid on the rising (oces = 1) or falling edge (oces = 0) of sclk. pbeo 24 o prbs bit error output. the receiver will constantly search for a 2 15 -1 or a 2 20 -1 prbs depending on the ets bit setting (ccr1.7). remains high if out of synchroni zation with the prbs pattern. goes low when synchronized to the prbs pattern. any errors in the received pattern after synchronization will cause a positive going pulse (with same period as e1 or t1 clock) synchronous with rclk. prbs bit errors can also be reported to the ecr1 and ecr2 registers by setting ccr6.2 to a logic 1. rclk 40 o receive clock. buffered recovered clock from the line. synchronous to mclk in absence of signal at rtip and rring. rcl/ lotc 25 o receive carrier loss / loss of transmit clock. an output which will toggle high during a receive carrier loss (ccr2.7 = 0) or will toggle high if the tclk pin has not been toggled for 5 sec 2 sec (ccr2.7 = 1). ccr2.7 defaults to logic 0 when in hardware mode.
ds2148/q48 15 of 75 acronym pin i/o description rneg 39 o receive negative data. updated on the rising edge (ccr2.0 = 0) or the falling edge (ccr2.0 = 1) of rclk with the bipolar data out of the line interface. set nrze (ccr1.6) to a one for nrz applications. in nrz mode, data will be output on rpos while a received error will cause a positive-going pulse synchronous with rclk at rneg. see section 8.4 for details. rpos 38 o receive positive data. updated on the rising edge (ccr2.0 = 0) or the falling edge (ccr2.0 = 1) of rclk with bipolar data out of the line interface. set nrze (ccr1.6) to a one for nrz applications. in nrz mode, data will be output on rpos while a received error will cause a positive-going pulse synchronous with rclk at rneg. see section 8.4 for details. rtip/ rring 27/ 28 i receive tip and ring. analog inputs for clock recovery circuitry. these pins connect via a 1:1 transformer to the line. see section 7 for details. sclk 5 i serial clock. serial bus clock input. sdi 6 i serial data input. sampled on rising edge (ices = 0) or the falling edge (ices = 1) of sclk. sdo 7 o serial data output. valid on the falling edge (oces = 0) or the rising edge (oces = 1) of sclk. tclk 43 i transmit clock. a 2.048 mhz or 1.544 mhz primary clock. used to clock data through the transmit side formatter. can be sourced internally by mclk or rclk. see common control register 1 and figure 3-3. test 26 i 3-state control. set high to 3-state all outputs and i/o pins (including the parallel control port). set low for normal operation. useful in board level testing. tneg 42 i transmit negative data. sampled on the falling edge (ccr2.1 = 0) or the rising edge (ccr2.1 = 1) of tclk for data to be transmitted out onto the line. tpos 41 i transmit positive data. sampled on the falling edge (ccr2.1 = 0) or the rising edge (ccr2.1 = 1) of tclk for data to be transmitted out onto the line. ttip/ tring 34/ 37 o transmit tip and ring [ttip & tring]. analog line driver outputs. these pins connect via a st ep-up transformer to the line. see section 7 for details. v dd 21/ 36 - positive supply. 5.0v 5% vsm 20 i voltage supply mode. should be tied high for 5v operation v ss 22/ 35 - signal ground.
ds2148/q48 16 of 75 pin assignment in hardware mode table 4-4a DS2148T pin # ds2148g pin# i/o hardware mode 1 c3 i egl 2 c2 i ets 3 b1 i nrze 4 d2 i sclke 5 c1 i l2 6 d3 i l1 7 d1 i/o l0 8 e1 i dja 9 f2 i jamux 10 f1 i jas 11 g1 i hbe 12 e3 i/o ces 13 f3 i/o tpd 14 g2 i/o tx0 15 f4 i/o tx1 16 g3 i/o loop0 17 e4 i/o loop1 18 g4 i/o mm0 19 f5 i/o mm1 20 g5 i vsm 21 f6 - v dd 22 g6 - v ss 23 e5 i/o rt1 24 e6 o pbeo 25 f7 o rcl 26 d6 i test 27 d5 i rtip 28 d7 i rring 29 c6 i hrst* 30 c7 i mclk 31 b6 o bpclk 32 b7 i bis0 33 a7 i bis1 34 c5 o ttip 35 b5 - v ss 36 a6 - v dd 37 b4 o tring 38 c4 o rpos 39 a4 o rneg 40 b3 o rclk 41 a3 i tpos 42 b2 i tneg 43 a2 i tclk 44 a1 i rt0
ds2148/q48 17 of 75 pin descriptions in hardware mode (sorted by pin name, DS2148T pin numbering) table 4-4b acronym pin i/o description bis0/ bis1 32/ 33 i bus interface select bits 0 & 1. used to select bus interface option. bis0 = 1 and bis1 = 1 selects hardware mode. bpclk 31 o back plane clock. 16.384 mhz output. ces 12 i receive & transmit clock edge select. selects which rclk edge to update rpos and rneg a nd which tclk edge to sample tpos and tneg. 0 = update rneg/rpos on rising edge of rclk; sample tpos/tneg on falling edge of tclk 1 = update rneg/rpos on fallin g edge of rclk; sample tpos/tneg on rising edge of tclk dja 8 i disable jitter attenuator. 0 = jitter attenuator enabled 1 = jitter attenuator disabled egl 1 i receive equalizer gain limit. this pin controls the sensitivity of the receive equalizer. egl e1 (ets = 0) 0 = -12db (short haul) 1 = -43db (long haul) egl t1 (ets = 1) 0 = -36db (long haul) 1 = -30db (limited long haul) ets 2 i e1/t1 select. 0 = e1 1 = t1 hbe 11 i receive & transmit hdb3/b8zs enable. 0 = enable hdb3 (e1)/b8zs (t1) 1 = disable hdb3 (e1)/b8zs (t1) hrst* 29 i hardware reset. bringing hrst* low will reset the ds2148. jamux 9 i jitter attenuator mux. controls the source for jaclk. see figure 3-1 and table 4-10. e1 (ets = 0) jamux mclk = 2.048 mhz 0 t1 (ets = 1) mclk = 2.048 mhz 1 mclk = 1.544 mhz 0 jas 10 i jitter attenuator select. 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side l0/l1/l2 7/ 6/ 5 i transmit liu waveshape select bits 0 & 1 [h/w mode]. these inputs determine the waveshape of the transmitter. see table 9-1 and table 9-2. loop0/ loop1 16/ 17 i loopback select bits 0 & 1 [h/w mode]. these inputs determine the active loopback mode (if any). see table 4-5.
ds2148/q48 18 of 75 acronym pin i/o description mclk 30 i master clock. a 2.048mhz (50ppm) clock source with ttl levels is applied at this pin. this clock is used internally for both clock/data recovery and for jitte r attenuation. use of a t1 1.544mhz clock source is optional. g.703 requires an accuracy of 50ppm for both t1 and e1. tr62411 and ansi specs require an accuracy of 32ppm for t1 interfaces. mm0/ mm1 18/ 19 i monitor mode select bits 0 & 1 [h/w mode]. these inputs determine if the receive equalizer is in a monitor mode. see table 4-8. na - i not assigned. should be tied low. nrze 3 i nrz enable [h/w mode]. 0 = bipolar data at rpos/rneg and tpos/tneg 1 = nrz data at rpos and tp os or tneg; rneg outputs a positive going pulse when device receives a bpv, cv, or exz. pbeo 24 o prbs bit error output. the receiver will constantly search for a qrss (t1) or a 2 15 -1 (e1) prbs depending on whether t1 or e1 mode is selected. remains high if out of synchronization with the prbs pattern. goes low when sy nchronized to the prbs pattern. any errors in the received pattern after synchronization will cause a positive going pulse (with same period as e1 or t1 clock) synchronous with rclk. rclk 40 o receive clock. buffered recovered clock from the line. synchronous to mclk in absence of signal at rtip and rring. rcl 25 o receive carrier loss. an output which will toggle high during a receive carrier loss. rneg 39 o receive negative data. updated on the rising edge (ces = 0) or the falling edge (ces = 1) of rclk with the bipolar data out of the line interface. set nrze to a one for nrz applications. in nrz mode, data will be output on rpos while a received error will cause a positive-going pulse synchronous with rclk at rneg. see section 8.4 for details. rpos 38 o receive positive data. updated on the rising edge (ces = 0) or the falling edge (ces = 1) of rclk with bipolar data out of the line interface. set nrze pin to a one for nrz applications. in nrz mode, data will be output on rpos while a received error will cause a positive-going pulse synchronous with rclk at rneg. see section 8.4 for details. rt0/ rt1 44/ 23 i receive liu termination select bits 0 & 1 [h/w mode]. these inputs determine the receive termination. see table 4-9. rtip/ rring 27/ 28 i receive tip and ring. analog inputs for clock recovery circuitry. these pins connect via a 1:1 transf ormer to the line. see section 7 for details. sclke 4 i receive & transmit synchronization clock enable. 0 = disable 2.048 mhz synchronization transmit and receive mode 1 = enable 2.048 mhz synchronization transmit and receive mode
ds2148/q48 19 of 75 acronym pin i/o description tclk 43 i transmit clock. a 2.048 mhz or 1.544 mhz primary clock. used to clock data through the transmit side formatter. test 26 i 3-state control. set high to 3-state all outputs and i/o pins (including the parallel control port). set low for normal operation. useful in board level testing. tneg 42 i transmit negative data. sampled on the falling edge (ces = 0) or the rising edge (ces = 1) of tclk for data to be transmitted out onto the line. tpd 13 i transmit power-down. 0 = normal transmitter operation 1 = powers down the transmitter and 3-states the ttip and tring pins tpos 41 i transmit positive data. sampled on the falling edge (ces = 0) or the rising edge (ces = 1) of tclk for data to be transmitted out onto the line. ttip/ tring 34/ 37 o transmit tip and ring [ttip & tring]. analog line driver outputs. these pins connect via a st ep-up transformer to the line. see section 7 for details. tx0/ tx1 14/ 15 i transmit data source select bits 0 & 1 [h/w mode]. these inputs determine the source of th e transmit data. see table 4-6. v dd 21/ 36 - positive supply. 5.0v 5% vsm 20 i voltage supply mode. should be tied high for 5v operation v ss 22/ 35 - signal ground. notes: 1) g.703 requires an accuracy of 50ppm for bot h t1 and e1. tr62411 and ansi specs require an accuracy of 32ppm for t1 interfaces. 2) * denotes active low.
ds2148/q48 20 of 75 loop back control in hardware mode table 4-5 loopback symbol control bit loop1 loop0 remote loop back rlb ccr6.6 1 1 local loop back llb ccr6.7 1 0 analog loop back alb ccr6.4 0 1 no loop back ? ? 0 0 transmit data control in hardware mode table 4-6 transmit data symbol control bit tx1 tx0 transmit unframed all ones tua1 ccr3.7 1 1 transmit alternating ones and zeros taoz ccr3.5 1 0 transmit prbs tprbse ccr3.4 0 1 tpos and tneg ? ? 0 0 receive sensitivity settings table 4-7 egl (ccr4.4) ets (ccr1.7) receive sensitivity 0 0 (e1) - 12db (short haul) 1 0 (e1) -43db (long haul) 1 1 (t1) -30db (limited long haul) 0 1 (t1) -36db (long haul) monitor gain settings table 4-8 mm1 (ccr5.5) mm0 (ccr5.4) internal linear gain boost (db) 0 0 normal operation (no boost) 0 1 20 1 0 26 1 1 32 internal rx termination select table 4-9 rt1 (ccr5.1) rt0 (ccr5.0) internal receive termination configuration 0 0 internal receive-side termination disabled 0 1 internal receive-side 120 enabled 1 0 internal receive-side 100 enabled 1 1 internal receive-side 75 enabled mclk selection table 4-10 mclk jamux (ccr1.3) ets (ccr1.7) 2.048mhz 0 0 2.048mhz 1 1 1.544mhz 0 1
ds2148/q48 21 of 75 parallel port mode pinout (bis1 = 0, bis0 = 1 or 0) figure 4-1 serial port mode pinout (bis1 = 1, bis0 = 0) figure 4-2 1 cs* 2 na 3 na 4 na 5 sclk 6 sdi 7 sdo 8 ices 9 oces 10 na 11 na bis1 33 bis0 32 bpclk 31 mclk 30 hrst* 29 rring 28 rtip 27 test 26 rcl/lotc 25 pbeo 24 int* 23 34 ttip 35 vss 36 vdd 37 tring 38 rpos 39 rneg 40 rclk 41 tpos 42 tneg 43 tclk 44 pbts vss 22 vdd 21 vsm 20 na 19 na 18 na 17 na 16 na 15 na 14 na 13 na 12 ds2148 serial port operation (note: tie all na pins low) tie high tie low t i e l o w t i e h i g h 1 cs* 2 rd (ds) 3 wr* (r/w*) 4 ale (as) 5 na 6 na 7 a4 8 a3 9 a2 10 a1 11 a0 bis1 33 bis0 32 bpclk 31 mclk 30 hrst* 29 rring 28 rtip 27 test 26 rcl/lotc 25 pbeo 24 int* 23 34 ttip 35 vss 36 vdd 37 tring 38 rpos 39 rneg 40 rclk 41 tpos 42 tneg 43 tclk 44 pbts vss 22 vdd 21 vsm 20 ad0/d0 19 ad1/d1 18 ad2/d2 17 ad3/d3 16 ad4/d4 15 ad5/d5 14 ad6/d6 13 ad7/d7 12 ds2148 parallel port operation (note: tie all na pins low) tie low tie low (mux) or high (non-mux) t i e h i g h
ds2148/q48 22 of 75 hardware mode pinout (bis1 = 1, bis0 = 1) figure 4-3 5. hardware mode in hardware mode (bis1 = 1, bis0 = 1), pins 1-19, 23, 25, 31, and 44 are redefined to be used for initializing the ds2148. bpclk (pin 31) defaults to a 16.384mhz output when in hardware mode. the rcl/lotc (pin 25) is designated to rcl when in hardware mode. jabds ( ccr4.2) defaults to logic 0. the rhbe (ccr2.3) and thbe ( ccr2.2) control bits are combined and controlled by hbe at pin 11 while the rsclke (ccr5.3) and tsclke (ccr5.2) b its are combined and controlled by sclke at pin 4. tces (ccr2.1) and rces (ccr2.0) are combin ed and controlled by ces at pin 12. the transmitter functions are combined and controlled by tx1 (pin 15) and tx0 (pin 14). loop1 (pin 17) and loop0 (pin 16) control the loopback functions. all other control bits default to the logic 0 setting. 1 egl 2 ets 3 nrze 4 sclke 5 l2 6 l1 7 l0 8 dja 9 jamux 10 jas 11 hbe bis1 33 bis0 32 bpclk 31 mclk 30 hrst* 29 rring 28 rtip 27 test 26 rcl 25 pbeo 24 rt1 23 34 ttip 35 vss 36 vdd 37 tring 38 rpos 39 rneg 40 rclk 41 tpos 42 tneg 43 tclk 44 rt0 vss 22 vdd 21 vsm 20 mm1 19 mm0 18 loop1 17 loop0 16 tx1 15 tx0 14 tpd 13 ces 12 ds2148 hardware operation tie high tie high t i e h i g h
ds2148/q48 23 of 75 5.1 register map register map table 5-1 acronym register name r/w parallel port mode serial port mode see notes 2?5 (msb) (lsb) ccr1 common control register 1 r/w 00h b000 000a ccr2 common control register 2 r/w 01h b000 001a ccr3 common control register 3 r/w 02h b000 010a ccr4 common control register 4 r/w 03h b000 011a ccr5 common control register 5 r/w 04h b000 100a ccr6 common control register 6 r/w 05h b000 101a sr status register r 06h b000 110a imr interrupt mask register r/w 07h b000 111a rir1 receive information register 1 r 08h b001 000a rir2 receive information register 2 r 09h b001 001a ibcc in-band code control register r/w 0ah b001 010a tcd1 transmit code definition register 1 r/w 0bh b001 011a tcd2 transmit code definition register 2 r/w 0ch b001 100a rupcd1 receive up code definition register 1 r/w 0dh b001 101a rupcd2 receive up code definition register 2 r/w 0eh b001 110a rdncd1 receive down code definition register 1 r/w 0fh b001 111a rdncd2 receive down code definition register 2 r/w 10h b010 000a ecr1 error count register 1 r 11h b010 001a ecr2 error count register 2 r 12h b010 010a test1 test 1 r/w 13h b010 011a test2 test 2 r/w 14h b010 100a test3 test 3 r/w 15h b010 101a ? ? ? note 1 ? notes: 1) register addresses 16h to 1fh do not exist. 2) in the serial port mode, the lsb is on the right hand side. 3) in the serial port mode, data is read and written lsb first. 4) in the serial port mode, the a bit (the lsb) dete rmines whether the access is a read (a = 1) or a write (a = 0). 5) in the serial port mode, the b bit (the msb) determines whether the access is a burst access (b = 1) or a single register access (b = 0).
ds2148/q48 24 of 75 5.2 parallel port operation when using the parallel interface on the ds2148 (bis1 = 0) the user has the option for either multiplexed bus operation (bis1 = 0, bis0 = 0) or nonmultiple xed bus operation (bis1 = 0, bis0 = 1). the ds2148 can operate with either intel or motorola bus timing configurations. if the pbts pin is tied low, intel timing will be selected; if tied high, motorola timing will be selected. all motorola bus signals are listed in parenthesis (). see the timing diagrams in section 12 for more details. 5.3 serial port operation setting bis1 = 1 and bis0 = 0 enables the serial bus interface on the ds2148. port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. see section 12 for the ac timing of th e serial port. all serial port accesse s are lsb first. see figure 5-1, figure 5-2, figure 5-3, and figure 5-4 for more details. reading or writing to the internal registers requires writing one address/command byte prior to transferring register data. the first bit written (lsb) of the address/command byte specifies whether the access is a read (1) or a write (0). the next 5 bits identify the register address. bit 7 is reserved and must be set to 0 for proper operation. the last bit (msb) of the address/command byte is the burst mode bit. when the burst bit is enabled (b = 1) and a read operation is performed, addresse s 0 through 15h are read sequentially, starting at address 0h. and when the burst bit is enabled and a write operation is performed, addresses 0 through 16h are written sequentially, startin g at address 0h. burst operation is stopped once address 15h is read. see figure 5-5 and figure 5-6 for more details. all data transfers are initiate d by driving the cs* input low. when i nput clock-edge select (ices) is low, input data is latched on the rising edge of sclk and when ices is high, input data is latched on the falling edge of sclk. when output clock-edge select (oces) is low, data is output on the falling edge of sclk and when oces is high, data is output on the rising edge of sclk. data is held until the next falling or rising edge. all data transfers are terminated if the cs* input transitions high. port control logic is disabled and sdo is 3- stated when cs* is high.
ds2148/q48 25 of 75 serial port operation for read access (r=1) mode 1 figure 5-1 ices = 1 (sample sdi on the falling edge of sclk) oces = 1 (update sdo on rising edge of sclk) serial port operation for read access mode 2 figure 5-2 ices = 1 (sample sdi on the falling edge of sclk) oces = 0 (update sdo on falling edge of sclk) 123456789 10 11 12 13 14 15 16 1 a0 a1 a2 a3 a4 0b d1 d2 d3 d4 d5 d6 scl k sdi sdo cs* (lsb) (msb) d0 (lsb) d7 (msb) read access enabled 123456789 10 11 12 13 14 15 16 1 a0 a1 a2 a3 a4 0b d1 d2 d3 d4 d5 d6 sclk sdi sdo cs* (lsb) (msb) d0 (lsb) d7 (msb)
ds2148/q48 26 of 75 serial port operation for read access mode 3 figure 5-3 ices = 0 (sample sdi on the rising edge of sclk) oces = 0 (update sdo on falling edge of sclk) serial port operation for read access mode 4 figure 5-4 ices = 0 (sample sdi on the rising edge of sclk) oces = 1 (update sdo on rising edge of sclk) 123456789 10 11 12 13 14 15 16 1 a0 a1 a2 a3 a4 0b d1 d2 d3 d4 d5 d6 scl k sdi sdo cs* (lsb) (msb) d0 (lsb) d7 (msb) 123456789 10 11 12 13 14 15 16 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 1 a0 a1 a2 a3 a 4 0 b d0 d0 d0 d0 d0 d0 scl k sdi sdo cs* (lsb) (msb) d0 (lsb) (msb) d1 d2 d3 d4 d5 d6 d0 d7
ds2148/q48 27 of 75 serial port operation for write access (r=0) figure 5-5 modes 1 and 2 ices = 1 (sample sdi on the falling edge of sclk) serial port operation for write access (r=0) figure 5-6 modes 3 and 4 ices = 0 (sample sdi on the rising edge of sclk) 123456789 10 11 12 13 14 15 16 sclk cs* 0 a0 a1 a2 a3 a4 0b (msb) sdi sdo d1 d2 d3 d4 d5 d7 (lsb) (msb) do d6 (lsb) write access enabled 123456789 10 11 12 13 14 15 16 sclk cs* 0 a 0a1 a 2a3 a 4 0b (msb) sdi sdo d1 d2 d3 d4 d5 d7 (lsb) (msb) do d6 (lsb) write access enabled
ds2148/q48 28 of 75 6. control registers ccr1 (00h): common control register 1 (msb) (lsb) ets nrze rcla ecue jamux ttoj ttor lotcmc symbol position description ets ccr1.7 e1/t1 select. 0 = e1 1 = t1 nrze ccr1.6 nrz enable. 0 = bipolar data at rpos/rneg and tpos/tneg 1 = nrz data at rpos and tp os or tneg; rneg outputs a positive going pulse when device receives a bpv, cv, or exz. see figure 3-2 and figure 3-3. rcla ccr1.5 receive carrier loss alternate criteria. 0 = rcl declared upon 255 (e1) or 192 (t1) consecutive zeros 1 = rcl declared upon 2048 (e1) or 1544 (t1) consecutive zeros ecue ccr1.4 error counter update enable. a 0 to 1-transition forces the next clock cycle to load the error counter registers with the latest counts and reset the c ounters. the user must wait a minimum of two clocks cycles (976ns for e1 and 1296ns for t1) before reading the error count registers to allow for a proper update. see section 6 and figure 3-2 for details. jamux ccr1.3 jitter attenuator mux. controls the source for jaclk. see figure 3-1. 0 = jaclk sourced from mclk (2.048mhz or 1.544mhz at mclk) 1 = jaclk sourced from internal pll (2.048mhz at mclk) ttoj ccr1.2 tclk to jaclk. internally connects tclk to jaclk. see figure 3-3. 0 = disabled 1 = enabled ttor ccr1.1 tclk to rclk. internally connects tclk to rclk . see figure 3-3. 0 = disabled 1 = enabled lotcmc ccr1.0 loss of transmit clock mux control. determines whether the transmit logic should switch to jaclk if the tclk input should fail to transition. see figure 3-3. 0 = do not switch to jaclk if tclk stops 1 = switch to jaclk if tclk stops
ds2148/q48 29 of 75 mclk selection table 6-1 mclk jamux (ccr1.3) ets (ccr1.7) 2.048mhz 0 0 2.048mhz 1 1 1.544mhz 0 1 ccr2 (01h): common control register 2 (msb) (lsb) p25s n/a scld clds rhbe thbe tces rces symbol position description p25s ccr2.7 pin 25 select. forced to logic 0 in hardware mode. 0 = toggles high during a receive carrier loss condition 1 = toggles high if tclk does not transition for at least 5 s. - ccr2.6 not assigned. should be set to zero when written to. scld ccr2.5 short circuit limit disable (ets = 0). controls the 50ma (rms) current limiter. 0 = enable 50ma current limiter 1 = disable 50ma current limiter clds ccr2.4 custom line driver select. setting this bit to a one will redefine the operation of the transmit line driver. when this bit is set to a one and ccr4.5 = ccr4.6 = ccr4.7 = 0, then the device will generate a square wave at the ttip and tring outputs instead of a normal waveform. when this bit is set to a one and ccr4.5 = ccr4.6 = ccr4.7 0, then the device will force ttip and tring outputs to become open drain drivers instead of their normal push-pull operation. this bit should be set to zero for normal operation of the device. contact the factory for more details on how to use this bit. rhbe ccr2.3 receive hdb3/b8zs enable. see figure 3-2. 0 = enable hdb3 (e1)/b8zs (t1) 1 = disable hdb3 (e1)/b8zs (t1) thbe ccr2.2 transmit hdb3/b8zs enable. see figure 3-3 . 0 = enable hdb3 (e1)/b8zs (t1) 1 = disable hdb3 (e1)/b8zs (t1) tces ccr2.1 transmit clock edge select. selects which tclk edge to sample tpos and tneg. see figure 3-3. 0 = sample tpos and tneg on falling edge of tclk 1 = sample tpos and tneg on rising edge of tclk rces ccr2.0 receive clock edge select. selects which rclk edge to update rpos and rneg. see figure 3-2. 0 = update rpos and rneg on rising edge of rclk 1 = update rpos and rneg on falling edge of rclk
ds2148/q48 30 of 75 ccr3 (02h): common control register 3 (msb) (lsb) tua1 atua1 taoz tprbse tlce lirst ibpv ibe symbol position description tua1 ccr3.7 transmit unframed all ones. the polarity of this bit is set such that the device will transmit an all ones pattern on power- up or device reset. this bit must be set to a one to allow the device to transmit data. the transmission of this data pattern is always timed off of the jaclk (see figure 3-1). 0 = transmit all ones at ttip and tring 1 = transmit data normally atua1 ccr3.6 automatic transmit unframed all ones. automatically transmit an unframed all ones pattern at ttip and tring during a receive carrier loss (rcl) condition or a receive all ones condition. 0 = disabled 1 = enabled taoz ccr3.5 transmit alternate ones and zeros. transmit a ?101010? pattern at ttip and tring. th e transmission of this data pattern is always timed off of tclk (figure 3-1). 0 = disabled 1 = enabled tprbse ccr3.4 transmit prbs enable. transmit a 2 15 - 1 (e1) or a 2 20 - 1 (t1) prbs at ttip and tring. see figure 3-3. 0 = disabled 1 = enabled tlce ccr3.3 transmit loop code enable. enables the transmit side to transmit the loop up code in the transmit code definition registers (tcd1 and tcd2). see section 6 and figure 3-3 for details. 0 = disabled 1 = enabled lirst ccr3.2 line interface reset. setting this bit from a zero to a one will initiate an internal reset that resets the clock recovery state machine and re-centers the jitter attenuator. normally this bit is only toggled on power-up. must be cleared and set again for a subsequent reset. ibpv ccr3.1 insert bpv. a 0 to 1 transition on this bit will cause a single bipolar violation (bpv) to be inserted into the transmit data stream. once this bit has been toggled from a 0 to a 1, the device waits for the next occurrence of three consecutive ones to insert the bpv. this bit must be cleared and set again for a subsequent error to be inserted. see figure 3-3. ibe ccr3.0 insert bit error. a 0 to 1 transition on this bit will cause a single logic error to be inserted into the transmit data stream. this bit must be cleared and set again for a subsequent error to be inserted. see figure 3-3.
ds2148/q48 31 of 75 6.1 device power-up and reset the ds2148 will reset itself upon powe r-up, setting all writeable register s to 00h and clearing the status and information registers. ccr3.7 (tua1) = 0 results in the liu transmitting unframed all ones. after the power supplies have settled follo wing power-up, initialize all control re gisters to the desired settings, then toggle the lirst bit (ccr3.2). the ds2148 can be reset at anytime to the default settings by bringing hrst* (pin 29) low (level triggered) or by powering down and powering up again. ccr4 (03h): common control register 4 (msb) (lsb) l2 l1 l0 egl jas jabds dja tpd symbol position description l2 ccr4.7 line build out select bit 2. sets the transmitter build out (table 9-1 for e1 and table 9-2 for t1) l1 ccr4.6 line build out select bit 1. sets the transmitter build out (table 9-1 for e1 and table 9-2 for t1) l0 ccr4.5 line build out select bit 0. sets the transmitter build out (table 9-1 for e1 and table 9-2 for t1) egl ccr4.4 receive equalizer gain limit. this bit controls the sensitivity of the receive equalizer (table 6-2) jas ccr4.3 jitter attenuator select. 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side jabds ccr4.2 jitter attenuator buffer depth select. 0 = 128 bits 1 = 32 bits (use for delay sensitive applications) dja ccr4.1 disable jitter attenuator. 0 = jitter attenuator enabled 1 = jitter attenuator disabled tpd ccr4.0 transmit power-down. 0 = normal transmitter operation 1 = powers down the transmitter and 3-states the ttip and tring pins receive sensitivity settings table 6-2 egl (ccr4.4) ets (ccr1.7) receive sensitivity 0 0 (e1) -12db (short haul) 1 0 (e1) -43db (long haul) 1 1 (t1) -30db (limited long haul) 0 1 (t1) -36db (long haul)
ds2148/q48 32 of 75 ccr5 (04h): common control register 5 (msb) (lsb) bpcs1 bpcs0 mm1 mm0 rsclke tsclke rt1 rt0 symbol position description bpcs1 ccr5.7 back plane clock select 1. see table 6-3 for details. bpcs0 ccr5.6 back plane clock select 0. see table 6-3 for details. mm1 ccr5.5 monitor mode 1. see table 6-4. mm0 ccr5.4 monitor mode 0. see table 6-4. rsclke ccr5.3 receive synchronization clock enable. this control bit determines wh ether the line receiver should handle normal t1/e1 signals or a synchronized signal. e1 mode: 0 = receive normal e1 signal (section 6 of g.703) 1 = receive 2.048 mhz synchronization signal (section 10 of g.703) t1 mode: 0 = receive normal t1 signal 1 = receive 1.544 mhz synchronization signal tsclke ccr5.2 transmit synchroniz ation clock enable. this control bit determines whether the transmitter should transmit normal t1/e1 signals or a synchronized signal. e1 mode: 0 = transmit normal e1 signal (section 6 of g.703) 1 = transmit 2.048 mhz synchronization signal (section 10 of g.703) t1 mode: 0 = transmit normal t1 signal 1 = transmit 1.544 mhz synchronization signal rt1 ccr5.1 receive termination 1. see table 6-5 for details. rt0 ccr5.0 receive termination 0 . see table 6-5 for details. back plane clock select table 6-3 bpcs1 (ccr5.7) bpcs0 (ccr5.6) bpclk frequency 0 0 16.384mhz 0 1 8.192mhz 1 0 4.096mhz 1 1 2.048mhz monitor gain settings table 6-4
ds2148/q48 33 of 75 mm1 (ccr5.5) mm0 (ccr5.4) internal linear gain boost (db) 0 0 normal operation (no boost) 0 1 20 1 0 26 1 1 32
ds2148/q48 34 of 76 internal rx termination select table 6-5 rt1 (ccr5.1) rt0 (ccr5.0) internal receive termination configuration 0 0 internal receive-side termination disabled 0 1 internal receive-side 120 enabled 1 0 internal receive-side 100 enabled 1 1 internal receive-side 75 enabled ccr6 (05h): common control register 6 (msb) (lsb) llb rlb arlbe alb rjab ecrs2 ecrs1 ecrs0 symbol position description llb ccr6.7 local loopback. in local loopback (llb), transmit data will be looped back to the receive path passing through the jitter attenuator if it is enabled. data in the transmit path will act as normal. see figure 3-1 (ds2148 block diagram figure 3-1 and section 8-2.2 for details. 0 = loopback disabled 1 = loopback enabled rlb ccr6.6 remote loopback. in remote loopback (rlb), data output from the clock/data recovery circuitry will be looped back to the transmit path passing through the jitter attenuator if it is enabled. data in the receive path will act as normal while data presented at tpos and tneg will be ignored. see figure 3-1 (ds2148 block diagram figure 3-1 and section 8-2.1 for details. 0 = loopback disabled 1 = loopback enabled arlbe ccr6.5 automatic remote loopback enable and reset. when this bit is set high, the device will automatically go into remote loopback when it detects loop-up code programmed into the receive loop-up code defin ition registers (rupcd1 and rupcd2) for a minimum of 5 seconds and it will also set the rir2.1 status bit. once in a rlb state, it will remain in this state until it has detected the loop code programmed into the receive loop-down code defin ition registers (rdncd1 and rdncd2) for a minimum of 5 seconds at which point it will force the device out of rlb and clear rir2.1. toggling this bit from a 1 to a 0 can reset the automatic rlb circuitry. the action of the automatic remote loopback circuitry is logically or?ed with the rlb (ccr6.6) cont rol bit (i.e., either one can cause a rlb to occur). alb ccr6.4 analog loopback. in analog loopback (alb), signals at ttip and tring will be internally connected to rtip and rring. the incoming signals, from the line, at rtip and rring will be ignored. the signals at ttip and tring will be transmitted as normal. see figure 3-1 (ds2148 block diagram
ds2148/q48 35 of 76 symbol position description figure 3-1 and section 8-2.3 for more details. 0 = loopback disabled 1 = loopback enabled rjab ccr6.3 rclk jitter attenuator bypass. this control bit allows the recovered received clock a nd data to bypass the jitter attenuation while still allowing the bpclk output to use the jitter attenuator. see figure 3-1 and section 9-1 for details. 0 = disabled 1 = enabled ecrs2 ccr6.2 error count register select 2. see section 8.4 for details. ecrs1 ccr6.1 error count register select 1. see section 8.4 for details. ecrs0 ccr6.0 error count register select 0. see section 8.4 for details. 7. status registers there are three registers that contain information on the current real-time status of the device, status register (sr), and receive information registers 1 and 2 (rir1/rir2). when a particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. some of the bits in sr, rir1, and rir2 are latched bits and some are real-time bits. the register descriptions below list which status bits are latched and which are real-time bits. for latched status bits, when an event or an alarm occurs the bit is set to a one and will remain set until the user reads that bit. the bit will be cleared when it is read and it will not be set again until the event has occurred again. two of the latched status bits (rua1 & rcl) will remain set after reading if the alarm is still present. the user will always precede a read of any of the three status registers with a write. the byte written to the register will inform the ds2148 which bits the user wishes to read and have cleared. the user will write a byte to one of these registers with a one in the bit positions to be read and a zero in the other bit positions. when a one is written to a bit location, that location will be updated with the latest information. when a zero is written to a bit position, that bit pos ition will not be updated and the previous value will be held. a write to the status and information registers will be immediately followed by a read of the same register. the read result should be logically and? ed with the mask byte that was just written and this value should be written back in to the same register to ensure th at bit does indeed clear. this second write step is necessary because the alarms and events in the status registers occur asynchronously with respect to their access via the parallel port. this write-read-write scheme allows an external microcontroller or microprocessor to i ndividually poll certain bits without disturbing the other bits in the register. this operation is key in controlling th e ds2148 with higher-order software languages. the bits in the sr register have the unique ability to initiate a hardware interrupt via the int* output pin. each of the alarms and events in the sr can be either masked or unmasked from the interrupt pin via the interrupt mask register (imr). the interrupts caused by the rcl, rua1, and lotc bits in sr act differently than the interrupts caused by the other stat us bits in sr. the rcl, rua1 and lotc bits will force the int* pin low whenever they change state (i.e., go active or inactive). the int* pin will be allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur even if the alarm is still present. the other status bits in sr can force the int* pin low when they are set. the int* pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
ds2148/q48 36 of 75 received alarm criteria table 7-1 alarm e1/t1 set criteria clear criteria rua1 e1 less than two zeros in two frames (512 bits) more than two zeros in two frames (512 bits) rua1 t1 over a 3ms window, five or less zeros are received over a 3ms window, six or more zeros are received rcl 1 e1 255 (or 2048) 2 consecutive zeros received (g.775) in 255 bit times, at least 32 ones are received rcl 1 t1 192 (or 1544) 2 consecutive zeros are received 14 or more ones out of 112 possible bit positions are received starting with the first one received notes: 1) receive carrier loss (rcl) is also known as loss-of-signal (los) or red alarm in t1. 2) see ccr1.5 for details. sr (06h): status register (msb) (lsb) lup ldn lotc rua1 rcl tcle tocd prbsd symbol position description lup (latched) sr.7 loop up code detected. set when the loop up code defined in registers rupcd1 and rupcd2 is being received. see section 6 for details. ldn (latched) sr.6 loop down code detected. set when the loop down code defined in registers rdncd1 a nd rdncd2 is being received. see section 6 for details. lotc (real time) sr.5 loss of transmit clock. set when the tclk pin has not transitioned for 5 sec ( 2 sec). will force the lotc pin high. rua1 (latched) sr.4 receive unframed all ones. set when an unframed all ones code is received at rring and rtip. see table 7-1for details. rcl (latched) sr.3 receive carrier loss. set when a receive carrier loss condition exists at rring and rtip. see table 7-1for details. tcle (real time) sr.2 transmit current limit exceeded. set when the 50ma (rms) current limiter is activated whether the current limiter is enabled or not. tocd (real time) sr.1 transmit open circuit detect. set when the device detects that the ttip and tring outputs are open circuited. prbsd (real time) sr.0 prbs detect. set when the receive-side detects a 2 15 -1 (e1) or a 2 20 -1 (t1) pseudo random b it sequence (prbs).
ds2148/q48 37 of 75 imr (07h): interrupt mask register (msb) (lsb) lup ldn lotc rua1 rcl tcle tocd prbsd symbol position description lup imr.7 loop up code detected. 0 = interrupt masked 1 = interrupt enabled ldn imr.6 loop down code detected. 0 = interrupt masked 1 = interrupt enabled lotc imr.5 loss of transmit clock. 0 = interrupt masked 1 = interrupt enabled rua1 imr.4 receive unframed all ones. 0 = interrupt masked 1 = interrupt enabled rcl imr.3 receive carrier loss. 0 = interrupt masked 1 = interrupt enabled tcle imr.2 transmit current limiter exceeded. 0 = interrupt masked 1 = interrupt enabled tocd imr.1 transmit open circuit detect. 0 = interrupt masked 1 = interrupt enabled prbsd imr.0 prbs detection. 0 = interrupt masked 1 = interrupt enabled
ds2148/q48 38 of 75 rir1 (08h): receive information register 1 (msb) (lsb) zd 16zd hbd rclc rua1c jalt n/a n/a symbol position description zd (latched) rir1.7 zero detect. set when a string of at least four (ets = 0) or eight (ets = 1) consecutive zeros (regardless of the length of the string) have been received. will be cleared when read. 16zd (latched) rir1.6 sixteen zero detect. set when at least 16 consecutive zeros (regardless of the length of the string) have been received. will be cleared when read. hbd (latched) rir1.5 hdb3/b8zs word detect. set when an hdb3 (ets = 0) or b8zs (ets = 1) code word is detected independent of whether the receive hdb3/b8zs mode (ccr4.6) is enabled. will be cleared when read. useful for automatically setting the line coding. rclc (latched) rir1.4 receive carrier loss clear. set when the rcl alarm has met the clear criteria defined in table 7-1. will be cleared when read. rua1c (latched) rir1.3 receive unframed all ones clear. set when the unframed all ones signal is no longer detected. will be cleared when read. see table 7-1. jalt (latched) rir1.2 jitter attenuator limit trip. set when the jitter attenuator fifo reaches to within 4 bits of its useful limit. will be cleared when read. useful for debuggin g jitter attenuatio n operation. n/a rir1.1 not assigned. could be any value when read. n/a rir1.0 not assigned. could be any value when read.
ds2148/q48 39 of 75 rir2 (09h): receive information register 2 (msb) (lsb) rl3 rl2 rl1 rl0 n/a n/a arlb sec symbol position description rl3 (real time) rir2.7 receive level bit 3. see table 7-2. rl2 (real time) rir2.6 receive level bit 2. see table 7-2. rl1 (real time) rir2.5 receive level bit 1. see table 7-2. rl0 (real time) rir2.4 receive level bit 0. see table 7-2. n/a rir2.3 not assigned. could be any value when read. n/a rir2.2 not assigned. could be any value when read. arlb (real time) rir2.1 automatic remote loopback detected. this bit will be set to a one when the automatic remote loopback (rlb) circuitry has detected the presence of a loop up code for 5 seconds. it will remain set until the automatic rlb circuitry has detected the loop down code for 5 seconds. see section 6 for more details. this bit will be forced low when the automatic rlb circuitry is disabled (ccr6.5 = 0). sec (latched) rir2.0 one-second timer. this bit will be set to a one on one-second boundaries as timed by the device based on the rclk. it will be cleared when read. receive level indication table 7-2 rl3 rl2 rl1 rl0 receive level (db) 0 0 0 0 < -2.5 0 0 0 1 -2.5 to -5.0 0 0 1 0 -5.0 to -7.5 0 0 1 1 -7.5 to -10.0 0 1 0 0 -10.0 to -12.5 0 1 0 1 -12.5 to -15.0 0 1 1 0 -15.0 to -17.5 0 1 1 1 -17.5 to -20.0 1 0 0 0 -20.0 to -22.5 1 0 0 1 -22.5 to -25.0 1 0 1 0 -25.0 to -27.5 1 0 1 1 -27.5 to -30.0 1 1 0 0 -30.0 to -32.5 1 1 0 1 -32.5 to -35.0 1 1 1 0 -35.0 to -37.5 1 1 1 1 > -37.5
ds2148/q48 40 of 75 8. diagnostics 8.1 in-band loop code generation and detection the ds2148 has the ability to generate and detect a re peating bit pattern that is from one to eight or sixteen bits in length. to transmit a pattern, the user will load the pattern to be sent into the transmit code definition (tcd1 and tcd2) registers and select the proper length of the pattern by setting the tc0 and tc1 bits in the in-band code control (ibcc) register. when generating a 1, 2, 4, 8, or 16 bit pattern both the transmit code registers (tcd1 and tcd2) must be filled with the proper code. generation of a 1, 3, 5, or 7-bit pa ttern only requires tcd1 to be filled. once this is accomplished, the pattern will be transmitted as long as the tlce cont rol bit (ccr3.3) is enabled. as an example, if the user wished to transmit the standard ?loop up? c ode for channel service un its which is a repeating pattern of ...10000100001... then 80h would be loaded into tcd1 and the length would set using tc1 and tc0 in the ibcc register to 5 bits. the ds2148 can detect two separate repeating pattern s to allow for both a loop-up code and a loop-down code to be detected. the user will program the codes to be detected in the receive up code definition (rupcd1 and rupcd2) registers and the receive down code definition (rdncd1 and rdncd2) registers and the length of each pattern will be selected via the ibcc register. the ds2148 will detect repeating pattern codes with b it error rates as high as 1x10 -2 . the code detector ha s a nominal integration period of 48ms, hence, after about 48ms of receiving e ither code, the proper status bit (lup at sr.7 and ldn at sr.6) will be set to a one. normally codes are sent for a period of 5 seconds. it is recommended that the software poll the ds2148 every 100ms to 1000ms until 5 seconds has elapsed to ensure that the code is continuously present. ibcc (0ah): in?band code control register (msb) (lsb) tc1 tc0 rup2 rup1 rup0 rdn2 rdn1 rdn0 symbol position description tc1 ibcc.7 transmit code length definition bit 1. see table 8-1 tc0 ibcc.6 transmit code length definition bit 0. see table 8-1 rup2 ibcc.5 receive up code length definition bit 2. see table 8-2 rup1 ibcc.4 receive up code length definition bit 1. see table 8-2 rup0 ibcc.3 receive up code length definition bit 0. see table 8-2 rdn2 ibcc.2 receive down code length definition bit 2. see table 8-2 rdn1 ibcc.1 receive down code length definition bit 1. see table 8-2 rdn0 ibcc.0 receive down code length definition bit 0. see table 8-2
ds2148/q48 41 of 75 transmit code length table 8-1 tc1 tc0 length selected 0 0 5 bits 0 1 6 bits / 3 bits 1 0 7 bits 1 1 16 bits / 8 bits/4 bits / 2 bits / 1 bits receive code length table 8-2 rup2/ rdn2 rup1/ rdn1 rup0/ rdn0 length selected 0 0 0 1 bits 0 0 1 2 bits 0 1 0 3 bits 0 1 1 4 bits 1 0 0 5 bits 1 0 1 6 bits 1 1 0 7 bits 1 1 1 16 bits/8 bits tcd1 (0bh): transmit code definition register 1 (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 symbol position description c7 tcd1.7 transmit code definition bit 7. first bit of the repeating pattern. c6 tcd1.6 transmit code definition bit 6. c5 tcd1.5 transmit code definition bit 5. c4 tcd1.4 transmit code definition bit 4. c3 tcd1.3 transmit code definition bit 3. c2 tcd1.2 transmit code definition bit 2. a don?t care if a 5-bit length is selected. c1 tcd1.1 transmit code definition bit 1. a don?t care if a 5 or 6 bit length is selected. c0 tcd1.0 transmit code definition bit 0. a don?t care if a 5, 6 or 7 bit length is selected.
ds2148/q48 42 of 75 tcd2 (0ch): transmit code definition register 2 (msb) (lsb) c15 c14 c13 c12 c11 c10 c9 c8 symbol position description c15 tcd2.7 transmit code definition bit 15 c14 tcd2.6 transmit code definition bit 14 c13 tcd2.5 transmit code definition bit 13 c12 tcd2.4 transmit code definition bit 12 c11 tcd2.3 transmit code definition bit 11 c10 tcd2.2 transmit code definition bit 10 c9 tcd2.1 transmit code definition bit 9 c8 tcd2.0 transmit code definition bit 8 rupcd1 (0dh): receive up code definition register 1 (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 symbol position description c7 rupcd1.7 receive up code definition bit 7. first bit of the repeating pattern. c6 rupcd1.6 receive up code definition bit 6. a don?t care if a 1-bit length is selected. c5 rupcd1.5 receive up code definition bit 5. a don?t care if a 1 or 2 bit length is selected. c4 rupcd1.4 receive up code definition bit 4. a don?t care if a 1 to 3 bit length is selected. c3 rupcd1.3 receive up code definition bit 3. a don?t care if a 1 to 4 bit length is selected. c2 rupcd1.2 receive up code definition bit 2. a don?t care if a 1 to 5 bit length is selected. c1 rupcd1.1 receive up code definition bit 1. a don?t care if a 1 to 6 bit length is selected. c0 rupcd1.0 receive up code definition bit 0. a don?t care if a 1 to 7 bit length is selected.
ds2148/q48 43 of 75 rupcd2 (0eh): receive up code definition register 2 (msb) (lsb) c15 c14 c13 c12 c11 c10 c9 c8 symbol position description c15 rupcd2.7 receive up code definition bit 15 c14 rupcd2.6 receive up code definition bit 14 c13 rupcd2.5 receive up code definition bit 13 c12 rupcd2.4 receive up code definition bit 12 c11 rupcd2.3 receive up code definition bit 11 c10 rupcd2.2 receive up code definition bit 10 c9 rupcd2.1 receive up code definition bit 9 c8 rupcd2.0 receive up code definition bit 8 rdncd1 (0fh): receive down code definition register 1 (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 symbol position description c7 rdncd1.7 receive down code definition bit 7. first bit of the repeating pattern. c6 rdncd1.6 receive down code definition bit 6. a don?t care if a 1-bit length is selected. c5 rdncd1.5 receive down code definition bit 5. a don?t care if a 1 or 2 bit length is selected. c4 rdncd1.4 receive down code definition bit 4. a don?t care if a 1 to 3 bit length is selected. c3 rdncd1.3 receive down code definition bit 3. a don?t care if a 1 to 4 bit length is selected. c2 rdncd1.2 receive down code definition bit 2. a don?t care if a 1 to 5 bit length is selected. c1 rdncd1.1 receive down code definition bit 1. a don?t care if a 1 to 6 bit length is selected. c0 rdncd1.0 receive down code definition bit 0. a don?t care if a 1 to 7 bit length is selected.
ds2148/q48 44 of 75 rdncd2 (10h): receive down code definition register 2 (msb) (lsb) c15 c14 c13 c12 c11 c10 c9 c8 symbol position description c15 rdncd2.7 receive down code definition bit 15 c14 rdncd2.6 receive down code definition bit 14 c13 rdncd2.5 receive down code definition bit 13 c12 rdncd2.4 receive down code definition bit 12 c11 rdncd2.3 receive down code definition bit 11 c10 rdncd2.2 receive down code definition bit 10 c9 rdncd2.1 receive down code definition bit 9 c8 rdncd2.0 receive down code definition bit 8 8.2 loopbacks 8.2.1 remote loopback (rlb) when rlb (ccr6.6) is enabled, the ds2148 is placed into remote loopback. in this loopback, data from the clock/data recovery state mach ine will be looped back to the tran smit path passing through the jitter attenuator if it is enabled. the data at the rpos a nd rneg pins will be valid while data presented at tpos and tneg will be ignored (figure 3-1). if the automatic remote loop back enable (ccr6.5) is set to a one, the ds2148 will automatically go into remote loop back when it detects the loop up code programmed in the receive up code definition registers (rupcd1 and rupcd2) for a minimum of 5 seconds. when the ds2148 detects the loop down code programmed in the receive loop down code definition register s (rdncd1 and rdncd2) for a minimum of 5 seconds, the ds2148 will come out of remote loop back. setting arlbe to a zero also can disable the arlb. 8.2.2 local loopback (llb) when llb (ccr6.7) is set to a one, the ds2148 is pl aced into local loopback. in this loopback, data on the transmit-side will continue to be transmitted as normal. tclk and tpos/tneg will pass through the jitter attenuator (if enabled) and be output at rclk and rpos/rneg. incoming data from the line at rtip and rring will be ignored. if transmit unframed all ones (ccr3.7) is set to a one while in llb, ttip and tring will transmit all ones while tclk and tpos/tneg will be looped back to rclk and rpos/rneg (figure 3-1).
ds2148/q48 45 of 75 8.2.3 analog loopback (alb) setting alb (ccr6.4) to a one puts the ds2148 in analog loop back. signals at ttip and tring will be internally connected to rtip and rring. the incoming signals at rtip and rring will be ignored. the signals at ttip and tring will be transmitted as normal. (see figure 3-1.) 8.2.4 dual loopback (dlb) setting both ccr6.7 and ccr6.6 to a one, llb and rlb respectively, puts the ds2148 into dual loopback operation. the tclk and tpos/tneg si gnals will be looped back through the jitter attenuator (if enabled) and output at rclk and rpos /rneg. clock and data recovered from rtip and rring will be looped back to the transmit-side and out put at ttip and tring. this mode of operation is not available when implementing hardware operation. (see figure 3-1.) 8.3 prbs generation and detection setting tprbse (ccr3.4) = 1 enables the ds2148 to transmit a 2 15 -1 (e1) or a 2 20 -1 (t1) pseudo random bit sequence (prbs) depending on the ets bit setting in ccr1.7. the receive-side of the ds2148 will always search for these prbs patterns i ndependent of ccr3.4. the prbs bit error output (pbeo) will remain high until the receiver has synchroni zed to one of the two patterns (64 bits received without an error) at which time pbeo will go low and the prbsd bit in the status register (sr) will be set. once synchronized, any bit errors received will cause a positive going pulse at pbeo, synchronous with rclk. this output can be used with external circuitry to keep track of bit error rates during the prbs testing. setting ccr6.0 (ecrs) = 1 will allo w the prbs errors to be accumulated in the 16-bit counter in registers ecr1 and ecr2. the prbs sy nchronizer will remain in sync until it experiences 6 bit errors or more within a 64 bit span. both prbs patterns comply with the itu-t o.151 specifications. 8.4 error counter error count register 1 (ecr1) is the most significant word and ecr2 is the least significant word of a user-selectable 16-bit counter that records incoming errors including bipolar violations (bpv), code violations (cv), excessive zero vi olations (exz) and/or prbs errors . see table 8-3 and table 8-4 and figure 3-2 for details. definition of received errors table 8-3 error e1 or t1 definition of received errors bpv e1/t1 two consecutive marks with the same polarity. will ignore bpvs due to hdb3 and b8zs zero suppression when ccr2.3 = 0. typically used with ami coding (ccr2.3 = 1). itu-t o.161. cv e1 when hdb3 is enabled (ccr2.3 = 0) and the receiver detects two consecutive bpvs with the same polarity. itu-t o.161. exz e1 when four or more consecutive zeros are detected. exz t1 when receiving ami coded signal s (ccr2.3 = 1), detection of 16 or more zeros or a bpv. ansi t1.403 1999. when receiving b8zs coded signals ( ccr2.3 = 0), detection of 8 or more zeros or a bpv. ansi t1.403 1999. prbs e1/t1 a bit error in a received prbs pattern. see section 8.3 for details. itu-t o.151.
ds2148/q48 46 of 75 function of ecrs bits and rneg pin table 8-4 e1 or t1 (ccr1.7) ecrs2 (ccr6.2) ecrs1 (ccr6.1) ecrs0 (ccr6.0) rhbe (ccr2.3) function of ecr counters/rneg 1 0 0 0 0 x cvs 0 0 0 1 x bpvs (hdb3 code words not counted) 0 0 1 0 x cvs + exzs 0 0 1 1 x bpvs + exzs 1 0 x 0 0 bpvs (b8zs code words not counted) 1 0 x 1 0 bpvs + 8 exzs 1 0 x 0 1 bpvs 1 0 x 1 1 bpvs + 16 exzs x 1 x x x prbs errors 2 notes: 1) rneg outputs error data only when in nrz mode (ccr1.6 = 1). 2) prbs errors will always be output at pbeo independent of ecr control bits and nrz mode and will not be present at rneg. 8.4.1 error counter update a transition of the ecue (ccr1.4) control bit from 0 to 1 will update the ecr re gisters with the current values and reset the counters. ecue must be set back to zero and another 0 to 1 transition must occur for subsequent reads/resets of the ecr registers. note that the ds2148 can report errors at rneg when in nrz mode (ccr1.6 = 1) by outputting a pulse for each error occurrence. the counter saturates at 65,535 and will not rollover. ecr1 (11h): upper error count register 1 ecr2 (12h): lower error count register 2 (msb) (lsb) e15 e14 e13 e12 e11 e10 e9 e8 ecr1 e7 e6 e5 e4 e3 e2 e1 e0 ecr2 symbol position description e15 ecr1.7 msb of the 16-bit error count e0 ecr2.0 lsb of the 16-bit error count 8.5 error insertion when ibpv (ccr3.1) is transitioned from a zero to a one, the device waits for the next occurrence of three consecutive ones to insert a bpv. ibpv must be cleared and set again for another bpv error insertion. see figure 3-3 for details on the insertion of the bpv into the datastream. when ibe (ccr3.0) is transitioned from a zero to a one , the device will insert a logic error. ibe must be cleared and set again for another logic error inserti on. see figure 3-3 for details on the insertion of the logic error into the datastream.
ds2148/q48 47 of 75 9. analog interface 9.1 receiver the ds2148 contains a digital clock recovery system. the ds2148 coupl es to the receive e1 or t1 twisted pair (or coaxial cable in 75 ? e1 applications) via a 1:1 transfor mer. see table 9-3 or transformer details. figure 9-1, figure 9-2, and figu re 9-3 along with table 9-1 and table 9-2 show the receive termination requirements. the ds 2148 has the option of using internal termination resistors. the ds2148 is designed to be fully software-selectable for e1 and t1 without the need to change any external resistors for the receive-side. the receive- side will allow the user to configure the ds2148 for 75 ? , 100 ? , or 120 ? receive termination by setting the rt 1 (ccr5.1) and rt0 (ccr5.0) bits. when using the internal termination feat ure, the rr resistors should be 60 ? each (figure 9-1). if external termination is required, rt1 and rt0 should be set to 0 and both rr resistors in figure 9-1 will need to be 37.5 ? , 50 ? , or 60 ? each depending on the line impedance. the resultant e1 or t1 clock derived from the 2.048/ 1.544 pll (jaclk in figure 3-1) is internally multiplied by 16 via another internal pll and fed to the clock recovery system. the clock recovery system uses the clock from the pll circuit to form a 16 times oversampler, which is used to recover the clock and data. this oversampling technique offers outstanding performance to meet jitter tolerance specifications shown in figure 9-6. normally, the clock that is output at the rclk pin is the recovered clock from the e1 ami/hdb3 or t1 ami/b8zs waveform presented at the rtip and rring inputs. when no signal is present at rtip and rring, a receive carrier loss (rcl) condition will occur and the rclk will be derived from the jaclk source (figure 3-1). if the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the rclk to an approximate 50% duty cycle. if the jitter attenuator is either placed in the transmit path or is disabled, the rclk output can exhibit slightly shorter high cycles of the clock. this is due to the highly oversampled digital clock recovery circuitry. see the receive ac timing characteristics in section 12 for more details. the receive-side circuitry also contains a clock synthesizer which outputs a user configurable clock (up to 16.384mhz) synthesized to rclk at bpclk (pin 31). see table 6-3 for details on output clock frequencies at bpclk. in hardware mode , bpclk defaults to a 16.384mhz output. the ds2148 has a bypass mode for the receive side cl ock and data. this allows the bpclk to be derived from rclk after the jitter attenuator while the clock and data presented at rclk, rpos, and rneg go unaltered. this is intended for applications where the receive side jitter attenuation will be done after the liu. setting rjab (ccr6.3) to a logic 1 will enable the bypass. be sure that the jitter attenuator is in the receive path ( ccr4.3 = 0). see figure 3-1 for details. the ds2148 will report the signal strength at rtip and rring in 2.5db increments via rl3-rl0 located in the receive informati on register 2. this feature is helpful when trouble shooting line performance problems. see table 7-2 for details. monitor applications in both e1 and t1 require various flat gain settings for the receive-side circuitry. the ds2148 can be programmed to support these appli cations via the monitor mode control bits mm1 and mm0. when the monitor modes are enabled, th e receiver will tolerate normal line loss up to ?6db. see table 6-4 for details.
ds2148/q48 48 of 75 9.2 transmitter the ds2148 uses a set of laser-trimme d delay lines along with a precis ion digital-to-analog converter (dac) to create the waveforms that are transmitted onto the e1 or t1 line. the waveforms created by the ds2148 meet the latest etsi, itu, ansi, and at &t specifications. the user will select which waveform is to be generated by setting the ets bit (ccr1.7) for e1 or t1 operation, then programming the l2/l1/l0 bits in common control register 4 fo r the appropriate application. see table 9-1 and table 9-2 for the proper l2/l1/l0 settings. a 2.048mhz or 1.544mhz ttl clock is required at tc lk for transmitting data at tpos and tneg. itu specification g.703 requires an accuracy of 50ppm for both t1 and e1. tr62411 and ansi specs require an accuracy of 32ppm for t1 interfaces. the clock can be sourced internally by rclk or jaclk. see ccr1.2, ccr1.1, ccr1.0, and figure 3.3 for details. because of the nature of the ds2148 transmitter design, very l ittle jitter (less than 0.005 uipp broadband from 10hz to 100khz) is added to the jitter present on tclk. also, the waveforms created are independent of the duty cycle of tclk. the transmitter in the ds2148 couples to the e1 or t1 tr ansmit twisted pair (or coaxial cable in some e1 applications) via a 1:1.36 step-up transformer. in orde r for the device to create the proper waveforms, the transformer used must meet the specifications listed in table 9-3. the ds2148 has automatic short-circ uit limiter that limits the source current to 50ma (rms) into a 1 ? load. this feature can be disabled by setting th e scld bit (ccr2.5) = 1. when the current limiter is activated, tcle (sr.2) will be set even if short circuit limiter is disabled. the tpd bit (ccr4.0) will power-down the transmit line driver and 3-state the ttip and tring pi ns. the ds2148 also can detect when the ttip or tring outputs are open-circuited. when an open circuit is detected, tocd (sr.1) will be set. 9.3 jitter attenuator the ds2148 contains an onboard jitter attenuator that can be set to a depth of either 32 bits or 128 bits via the jabds bit (ccr4.2). in hardware mode the de pth is 128 bits and cannot be changed. the 128-bit mode is used in applications where large excursions of wander are expected. the 32-bit mode is used in delay sensitive applications. the characteristics of the attenuation are shown in figure 9-7. the jitter attenuator can be placed in either the receive path or the transmit path by appr opriately setting or clearing the jas bit (ccr4.3). also, the jitter attenuator can be disabled (in e ffect, removed) by setting the dja bit (ccr4.1). in order for the jitte r attenuator to operate properly, a 2.048mhz or 1.544mhz clock must be applied at mclk. itu specification g.703 require s an accuracy of 50ppm for both t1 and e1. tr62411 and ansi specs require an accuracy of 32ppm for t1 interfaces. there is an onboard pll for the jitter attenuator, which will convert the 2.048mhz clock to a 1.544mhz rate for t1 applications. setting jamux (ccr1.3) to a logic 0 bypasses this pll. onboard circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the tclk pin to create a smooth jitter free clock which is used to clock data out of the jitter attenuator fifo. it is acceptable to provide a gapped/bursty clock at the tclk pin if the jitter attenuator is placed on the transmit side. if the incoming jitter exceeds either 120 uipp (buffer depth is 128 bits) or 28 uipp (buffer depth is 32 bits), then the ds2148 will divide the internal nominal 32.768mhz (e1) or 24.704mhz (t1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overfl owing. when the device divides by either 15 or 17, it also sets the jitter attenuator limit trip (jalt) bit in the receive information register 1 (rir1).
ds2148/q48 49 of 75 9.4 g.703 synchronization signal the ds2148 is capable of receiving a 2.048mhz squa re-wave synchronization clock as specified in section 13 of itu g.703 (10/98). to use the ds2148 in this mode, set the receive synchronization clock enable (ccr5.3) = 1. the ds2148 can also transmit the 2.048mhz square-wave synchronization clock as specified in section 10 of g.703. to transmit the 2.048mhz clock, set the transmit synchronization clock enable (ccr5.2) = 1. line build out select for e1 in register ccr4 (ets = 0) table 9-1 l2 l1 l0 v dd application n return loss rt 0 0 0 5v 75 normal 1:1.36 nm 0 0 0 1 5v 120 normal 1:1.36 nm 0 1 0 0 5v 75 w/ high return loss 1:1.36 21 db 18 1 0 1 5v 120 w/ high return loss 1:1.36 21 db 27 note: see figure 9-1, figure 9-2, and figure 9-3. line build out select for t1 in register ccr4 (ets = 1) table 9-2 l2 l1 l0 v dd application n return loss rt 0 0 0 5v dsx-1 (0 to 133 feet) / 0 db csu 1:1.36 nm 0 0 0 1 5v dsx-1 (133 to 266 feet) 1:1.36 nm 0 0 1 0 5v dsx-1 (266 to 399 feet) 1:1.36 nm 0 0 1 1 5v dsx-1 (399 to 533 feet) 1:1.36 nm 0 1 0 0 5v dsx-1 (533 to 655 feet) 1:1.36 nm 0 1 0 1 5v -7.5db csu 1:1.36 nm 0 1 1 0 5v -15db csu 1:1.36 nm 0 1 1 1 5v -22.5db csu 1:1.36 nm 0 note: see figure 9-1, figure 9-2, and figure 9-3.
ds2148/q48 50 of 75 transformer specifications for 5v operation table 9-3 specification recommended value turns ratio 5v applications 1: 1(receive) and 1:1.36(transmit) 2% primary inductance 600 h minimum leakage inductance 1.0 h maximum interwinding capacitance 40pf maximum transmit transformer dc resistance primary (device side) secondary 1.2 maximum 1.2 maximum receive transformer dc resistance primary (device side) secondary 1.2 maximum 1.2 maximum
ds2148/q48 51 of 75 basic interface figure 9-1 notes: 1) all resistor values are 1%. 2) in e1 applications, the rt resistors are used to increase the transmitter return loss (table 9-1). no return loss is required for t1 applications. 3) the rr resistors should be set to 60 each if the internal receive-side termination feature is enabled. when this feature is disabled, rr = 37.5 for 75 , 60 for 120 e1 systems, or 50 for 100 t1 lines. 4) see table 9-1 and table 9-2 for the appropriate transmit transformer turns ratio (n). rtip rring ttip tring receive line n:1 (larger winding toward the network) ds2148 0.47f (non polarized) v dd (21) v ss (22) 0.1f v dd (36) v ss (35) 0.1f +v dd 0.01f 2.048mhz (this clock can also be 1.544mhz for t1 only applications) mclk 1:1 0.1f r r r r r t rt transmi t line 10f 10f
ds2148/q48 52 of 75 protected interface using internal receive termination figure 9-2 notes: 1) all resistor values are 1%. 2) c1 = c2 = 0.1f. 3) s is a 6v transient suppresser. 4) d1 to d8 are schottky diodes. 5) the fuses are optional to prevent ac power line crosses from compromising the transformers. 6) rp resistors exist to keep the fuses from openi ng during a surge. if they are used, then the 60 receive termination resistance must be adjusted to match the line impedance. 7) the rt resistors are used to increase the transmitter return loss (table 9-1). no return loss is required for t1 applications. 8) the transmit transformer turns ratio (n) would be 1:1.36 for 5v operation. 9) the 68 f is used to keep the local power plane potential within tolerance during a surge. rtip rring ttip tring receive line n:1 (larger winding toward the network) ds2148 0.47uf (non - polarized) vdd (21) vss (22) 0.1uf vdd (36) vss (35) 0.1uf +vdd 0.01uf 2.048mhz (this clock can also be 1.544mhz for t1 only applications) mclk +vdd s c1 d1 d2 d3 d4 1:1 rp fuse rp fuse +vdd c2 d5 d6 d7 d8 rt rt 68uf s (optional) transmi t line rp fuse rp fuse (optional) 10uf 10uf 0.1uf 60 60
ds2148/q48 53 of 75 protected interface using external receive termination figure 9-3 notes: 1) all resistor values are 1%. 2) c1 = 0.1f. 3) s is a 6v transient suppresser. 4) d1 to d4 are schottky diodes. 5) the fuses are optional to prevent ac power line crosses from compromising the transformers. 6) rp resistors exist to keep the fuses from opening during a surge. if they are used, then rr must be adjusted to match the line impedance. 7) rr = 37.5 for 75 , 60 for 120 e1 systems, or 50 for 100 t1 lines. 8) the rt resistors are used to increase the transmitter return loss (table 9-1). no return loss is required for t1 applications. 9) the transmit transformer turns ratio (n) would be 1:1.36 for 5v operation. 10) the 68 f is used to keep the local power plane potential within tolerance during a surge. rtip rring ttip tring receive line n:1 (larger winding toward the network) ds2148 0.47f (non- polarized) v dd (21) v ss (22) v dd (36) v ss (35) 2.048mhz (this clock can also be 1.544mhz for t1 only applications) mclk +v dd s c1 d1 d2 d3 d4 1:1 0.1f 470 470 rp fuse rp fuse r r r r rt rt (optional) transmi t line rp fuse rp fuse (optional) 0.1f 0.1f +v dd 0.01f 68f 10f 10f
ds2148/q48 54 of 75 e1 transmit pulse template figure 9-4 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 time (ns) scaled amplitude 50 100 150 200 250 -50 -100 -150 -200 -250 269ns 194ns 219ns (in 75 ohm systems, 1.0 on the scale = 2.37vpeak in 120 ohm systems, 1.0 on the scale = 3.00vpeak) g.703 template
ds2148/q48 55 of 75 t1 transmit pulse template figure 9-5 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 -500 -300 -100 0 300 500 700 -400 -200 200 400 600 100 time (ns) normalized amplitude t1.102/87, t1.403, cb 119 (oct. 79), & i.431 template -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05 ui time amp. maximum curve ui time amp. minimum curve
ds2148/q48 56 of 75 jitter tolerance figure 9-6 jitter attenuation figure 9-7 frequency (hz) unit intervals (uipp) 1k 100 10 1 0.1 10 100 1k 10k 100k ds2148 tolerance 1 tr 62411 (dec. 90) itu-t g.823 frequency (hz) 0db -20db -40db -60db 1 10 100 1k 10k jitter attenuation (db) 100k tr 62411 (dec. 90) prohibited area c u r v e b c ur ve a itu g.7xx prohibited area tbr12 prohibited area t1 e1
ds2148/q48 57 of 75 10. ds21q48 quad liu the ds21q48 is a quad version of the ds2148g utiliz ing cabga on carrier packaging technology. the four lius are controlled via the pa rallel port mode. serial and hardwa re modes are unavailable in this package. ds21q48 pin assignment table 10-1 ds21q48 pin# i/o parallel port mode j1 i connect to v ss k3 i connect to v ss j2 i rd*(ds*) h1 i wr*(r/w*) k2 i ale(as) k1 i/o a4 l1 i a3 h11 i a2 h12 i a1 g12 i a0 j10 i/o d7/ad7 h10 i/o d6/ad6 g11 i/o d5/ad5 j9 i/o d4/ad4 e3 i/o d3/ad3 d4 i/o d2/ad2 f3 i/o d1/ad1 d5 i/o d0/ad0 g4 i vsm k9 i/o int* k7 i test l9 i hrst* j6 i mclk l7 i bis0 m8 i bis1 m12 i pbts j3 i cs*1 d3 i cs*2 d10 i cs*3 k10 i cs*4 k5 o pbeo1 g3 o pbeo2 e10 o pbeo3 k8 o pbeo4 l6 o rcl/lotc1 d7 o rcl/lotc2 f9 o rcl/lotc3
ds2148/q48 58 of 75 ds21q48 pin# i/o parallel port mode j7 o rcl/lotc4 a1 i rtip1 a4 i rtip2 a7 i rtip3 a10 i rtip4 b2 i rring1 b5 i rring2 b8 i rring3 b11 i rring4 h4 o bpclk1 d6 o bpclk2 f10 o bpclk3 l8 o bpclk4 a2 o ttip1 a5 o ttip2 a8 o ttip3 a11 o ttip4 b3 o tring1 b6 o tring2 b9 o tring3 b12 o tring4 k4 o rpos1 e1 o rpos2 d11 o rpos3 k11 o rpos4 g2 o rneg1 e2 o rneg2 f11 o rneg3 m10 o rneg4 h3 o rclk1 f1 o rclk2 e11 o rclk3 l11 o rclk4 g1 i tpos1 f2 i tpos2 e12 i tpos3 m11 i tpos4 h2 i tneg1 m1 i tneg2 d12 i tneg3 k12 i tneg4 m2 i tclk1 l2 i tclk2 f12 i tclk3 l12 i tclk4
ds2148/q48 59 of 75 ds21q48 pin# i/o parallel port mode j5 - v dd1 d2 - v dd2 g9 - v dd3 m9 - v dd4 l5 - v dd1 e4 - v dd2 d8 - v dd3 j8 - v dd4 j4 - v ss1 d1 - v ss2 e9 - v ss3 l10 - v ss4 m4 - v ss1 f4 - v ss2 d9 - v ss3 h9 - v ss4
ds2148/q48 60 of 75 bga 12 x 12 pin layout figure 10-1 1 2 3 4 5 6 7 8 9 10 11 12 a rtip 1 ttip 1 nc rtip 2 ttip 2 nc rtip 3 ttip 3 nc rtip 4 ttip 4 nc b nc rring 1 tring 1 nc rring 2 tring 2 nc rring 3 tring 3 nc rring 4 tring 4 c nc nc nc nc nc nc nc nc nc nc nc nc d vss 2 vdd 2 cs* 2 d2/ ad2 d0/ ad0 bpclk 2 rcl/ lotc2 vdd 3 vss 3 cs* 3 rpos 3 tneg 3 e rpos 2 rneg 2 d3/ ad3 vdd 2 nc nc nc nc vss 3 pebo 3 rclk 3 tpos 3 f rclk 2 tpos 2 d1/ ad1 vss 2 nc nc nc nc rcl/ lotc3 bpclk 3 rneg 3 tclk 3 g tpos 1 rneg 1 pebo 2 vsm nc nc nc nc vdd 3 nc d5/ ad5 a0 h wr* (r/w*) tneg 1 rclk 1 bpclk 1 nc nc nc nc vss 4 d6/ ad6 a2 a1 j see note 2 rd* (ds*) cs* 1 vss 1 vdd 1 mclk rcl/ lotc4 vdd 4 d4/ ad4 d7/ ad7 nc nc k a4 ale (as) see note 2 rpos 1 pebo 1 nc test pebo 4 int* cs* 4 rpos 4 tneg 4 l a3 tclk 2 nc nc vdd 1 rcl/ lotc1 bis0 bpclk 4 hrst* vss 4 rclk 4 tclk 4 m tneg 2 tclk 1 nc vss 1 nc nc nc bis1 vdd 4 rneg 4 tpos 4 pbts notes: 1) shaded areas are signals common to all four devices. 2) connect to v ss .
ds2148/q48 61 of 75 11. dc characteristics absolute maximum ratings* voltage range on any pin relativ e to ground -1.0v to +6.0v operating temperature range for DS2148Tn -40 c to +85 c storage temperature range see j-std-020a specification * this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the opera tion sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time can affect reliability. recommended dc operating conditions (-40 c to +85 c) parameter symbol min typ max units notes logic 1 v ih 2.0 5.5 v logic 0 v il ?0.3 +0.8 v supply for 5v operation v dd 4.75 5 5.25 v 1 capacitance (t a = +25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf dc characteristics (-40 c to +85 c; v dd = 5.0v 5%) parameter symbol min typ max units notes input leakage i il ?1.0 +1.0 a 3 output leakage i lo 1.0 a 4 output current (2.4v) i oh ?1.0 ma output current (0.4v) i ol +4.0 ma supply current i dd - 95 125 ma 2, 5 notes: 1) applies to v dd . 2) tclk = mclk = 2.048mhz. 3) 0.0v < v in < v dd . 4) applied to int* when 3-stated. 5) power dissipation with ttip and tring driving a 30 load, for an all one?s data density.
ds2148/q48 62 of 75 thermal characteristics of ds21q48 bga package parameter min typ max notes ambient temperature -40oc - +85oc 1 junction temperature - - +125oc theta-ja ( ja ) in still air - +24oc/w - 2 theta-jc ( jc ) in still air - +4.1oc/w - 3 notes: 1) the package is mounted on a fou r-layer jedec-standard test board. 2) theta-ja ( ja ) is the junction to ambient thermal resistan ce, when the package is mounted on a four- layer jedec-standard test board. 3) while theta-jc ( jc ) is commonly used as the thermal paramete r that provides a correlation between the junction temperature (t j ) and the average temperature on top center of four of the chip-scale bga packages (t c ), the proper term is psi-jt. it is defined by: (t j - t c ) / overall package power the method of measurement of the thermal paramete rs is defined in eia/jedec-standard document eia-jesd51-2. theta-ja ( ja ) versus airflow forced air (m/s) theta-ja ( ja ) 0 24oc/w 1 21oc/w 2.5 19oc/w
ds2148/q48 63 of 75 12. ac characteristics ac characteristics?multi plexed parallel port (bis1 = 0, bis0 = 0) (-40 c to +85 c; v dd = 5.0v 5%) parameter symbol min typ max units notes cycle time t cyc 200 ns pulse width, ds low or rd* high pw el 100 ns pulse width, ds high or rd* low pw eh 100 ns input rise/fall times t r , t f 20 ns r/w* hold time t rwh 10 ns r/w* setup time before ds high t rws 50 ns cs* setup time before ds, wr* or rd* active t cs 20 ns cs* hold time t ch 0 ns read data hold time t dhr 10 50 ns write data hold time t dhw 0 ns muxed address valid to as or ale fall t asl 15 ns muxed address hold time t ahl 10 ns delay time ds, wr* or rd* to as or ale rise t asd 20 ns pulse width as or ale high pw ash 30 ns delay time, as or ale to ds, wr* or rd* t ased 10 ns output data delay time from ds or rd* t ddr 20 80 ns data setup time t dsw 50 ns see figure 12-1, figure 12-2, figure 12-3
ds2148/q48 64 of 75 intel bus read timing (pbts = 0, bis1 = 0, bis0 = 0) figure 12-1 intel bus write timing (pbts = 0, bis1 = 0, bis0 = 0) figure 12-2 ash pw t cyc t asd t asd pw pw eh el t t t t t t ahl ch cs asl ased cs* ad0-ad7 dhr t ddr ale rd* wr* ash pw t cyc t asd t asd pw pw eh el t t t t t t t ahl dsw dhw ch cs asl ased cs* ad0-ad7 rd* wr* ale
ds2148/q48 65 of 75 motorola bus timing (pbts = 1, bis1 = 0, bis0 = 0) figure 12-3 t asd ash pw t t asl ahl t cs t asl t t t dsw dhw t ch t t t ddr dhr rwh t ased pw eh t rws ahl pw el t cyc as ds ad0-ad7 (write) ad0-ad7 (read) r/w* cs*
ds2148/q48 66 of 75 ac characteristics?nonmultiplexed parallel port (bis1 = 0, bis0 = 1) (-40 c to +85 c; v dd = 5.0v 5%) parameter symbol min typ max units notes setup time for a0 to a4, valid to cs* active t1 0 ns setup time for cs* active to either rd*, wr*, or ds* active t2 0 ns delay time from either rd* or ds* active to data valid t3 75 ns hold time from either rd*, wr*, or ds* inactive to cs* inactive t4 0 ns hold time from cs* inactive to data bus 3-state t5 5 20 ns wait time from either wr* or ds* active to latch data t6 75 ns data setup time to either wr* or ds* inactive t7 10 ns data hold time from either wr* or ds* inactive t8 10 ns address hold from either wr* or ds* inactive t9 10 ns see figure 12-4, figure 12-5, figure 12-6, and figure 12-7
ds2148/q48 67 of 75 intel bus read timing (pbts = 0, bis1 = 0, bis0 = 1) figure12-4 intel bus write timing (pbts = 0, bis1 = 0, bis0 = 1) figure 12-5 address valid data valid a0 to a4 d0 to d7 wr* cs* rd* 0ns min. 0ns min. 75ns max. 0ns min. 5ns min. / 20ns max. t1 t2 t3 t4 t5 address valid a0 to a4 d0 to d7 rd* cs* wr* 0ns min. 0ns min. 75ns min. 0ns min. 10ns min. 10ns min. t1 t2 t6 t4 t7 t8
ds2148/q48 68 of 75 motorola bus read timing (pbt s = 1, bis1 = 0, bis0 = 1) figure 12-6 motorola bus write timing (pbts = 1, bis1 = 0, bis0 = 1) figure 12-7 address valid data valid a0 to a4 d0 to d7 r/w* cs* ds* 0ns min. 0ns min. 75ns max. 0ns min. 5ns min. / 20ns max. t1 t2 t3 t4 t5 address valid a0 to a4 d0 to d7 r/w* cs* ds* 0ns min. 0ns min. 75ns min. 0ns min. 10ns min. 10ns min. t1 t2 t6 t4 t7 t8
ds2148/q48 69 of 75 ac characteristics?serial port (bis1 = 1, bis0 = 0) (-40 c to +85 c; v dd = 5.0v 5%) parameter symbol min typ max units notes setup time cs* to sclk t css 50 ns setup time sdi to sclk t sss 50 ns hold time sclk to sdi t ssh 50 ns sclk high/low time t slh 200 ns sclk rise/fall time t srf 50 ns sclk to cs* inactive t lsc 50 ns cs* inactive time t cm 250 ns sclk to sdo valid t ssv 50 ns sclk to sdo 3-state t ssh 100 ns cs* inactive to sdo 3-state t csh 100 ns see figure 12-8 serial bus timing (bis1 = 1, bis0 = 0) figure 12-8 notes: 1) oces =1 and ices = 0. 2) oces = 0 and ices = 1. sclk 1 sclk 2 sdi cs* high z sdo t css t sss t ssh t srf t slh t lsc t cm t ssv t ssh t csh high z lsb lsb lsb msb msb msb
ds2148/q48 70 of 75 ac characteristics?receive side (-40 c to +85 c; v dd = 5.0v 5%) parameter symbol min typ max units notes rclk period t cp 488 648 ns ns 1 2 rclk pulse width t ch t cl 200 200 ns ns 3 3 rclk pulse width t ch t cl 150 150 ns ns 4 4 delay rclk to rpos, rneg, pbeo, rbpv valid t dd 50 ns notes: 1) e1 mode. 2) t1 or j1 mode. 3) jitter attenuator enabled in the receive path. 4) jitter attenuator disabled or enabled in the transmit path. receive side timing figure 12-9 notes: 1) rces = 1 (ccr2.0) or ces = 1. 2) rces = 0 (ccr2.0) or ces = 0. 3) rneg is in nrz mode (ccr1.6 = 1). t dd rpos, rneg rclk 2 cl t t cp ch t rclk 1 pbeo t dd bit error bpv/ exz/ cv prbs detector out of sync rneg 3 bpv/ exz/ cv
ds2148/q48 71 of 75 ac characteristics?transmit side (-40 c to +85 c; v dd = 5.0v 5%) parameter symbol min typ max units notes tclk period t cp 488 648 ns ns 1 2 tclk pulse width t ch t cl 75 75 ns ns tpos/tneg setup to tclk falling or rising t su 20 ns tpos/tneg hold from tclk falling or rising t hd 20 ns tclk rise and fall times t r , t f 25 ns see figure 12-10 notes: 1) e1 mode. 2) t1 or j1 mode. transmit side timing figure 12-10 notes: 1) tces = 0 (ccr2.1) or ces = 0. 2) tces = 1 (ccr2.1) or ces = 1. t f t r tpos, tneg t cl t ch cp t hd t su tclk 1 t tclk 2
ds2148/q48 72 of 75 13. mechanical dimensions dimensions are in millimeters see detail "a" suggested pad layout 44 pin tqfp, 10*10*1.0
ds2148/q48 73 of 75
ds2148/q48 74 of 75 13.1 mechanical dimensions?quad version top view (die side) bottom view (ball side) side view 0.76 z 2.60 ref 0.61 0.59 1.99 detail b 0.05 1.52 1.27 1.52 1.27 17.0 0 x 17.0 y a1 3 0.20 4 a1 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h i j k 13.97 detail a 13.97
ds2148/q48 75 of 75 detail a detail b 2.60 ref z 0.10 0.76 ref seating plane 2 / / 0.17 z / / 0.24 z 0.05 label thickness 0.76 ref 0.76 l 0.76 l x z y z solder ball

▲Up To Search▲

Price & Availability of DS2148T

	To Download DS2148T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .